Set 32-bit DMA mask for M3N and E3 #7
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The `dma_set_mask_and_coherent` does not always perform successfully and it also might fail. Ignoring this error and attempting to use DMA in case of failure will lead to undefined behavior. See for details: Documentation/core-api/dma-api-howto.rst Also, this patch puts the second call of the function inside the conditional block based on `IPMMU_MMU_SUPPORT` value. This is necessary to avoid a double function call when the `IPMMU_MMU_SUPPORT` is true. Signed-off-by: Sergii Piatakov <[email protected]>
With the current implementation, the MMNGR sets a 40-bit DMA bitmask (when IPMMU is enabled) regardless of the actual SoC. At the same time, M3N and E3 don't have 40-bit address space. IPMMU MMU supports physical address space in the legacy area. It is proposed to make changes that allow using the correct DMA bitmask for all devices. Signed-off-by: Oleksii Khramkov <[email protected]> Signed-off-by: Sergii Piatakov <[email protected]>
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With the current implementation, the MMNGR sets a 40-bit DMA bitmask (when IPMMU is enabled) regardless of the actual SoC. At the same time, M3N and E3 don't have 40-bit address space. IPMMU MMU supports physical address space in the legacy area. It is proposed to make changes that allow using the correct DMA bitmask for all devices.
This MR is based on #6 one.