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alanjian85alanjian85
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Implement the tiled rasterizer of triangles
1 parent 750fdef commit a9156a6

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11 files changed

+1428
-158
lines changed

11 files changed

+1428
-158
lines changed

‎src/main/scala/graphics/Graphics.scala

+44-3
Original file line numberDiff line numberDiff line change
@@ -11,9 +11,38 @@ class Graphics extends Module {
1111
val done = Output(Bool())
1212
})
1313

14+
val x0 = 512
15+
val y0 = 192
16+
17+
val x1 = 290
18+
val y1 = 576
19+
20+
val x2 = 734
21+
val y2 = 576
22+
23+
val dx0 = x1 - x0
24+
val dx1 = x2 - x1
25+
val dx2 = x0 - x2
26+
27+
val dy0 = y1 - y0
28+
val dy1 = y2 - y1
29+
val dy2 = y0 - y2
30+
31+
val re0 = x0 * dy0 - y0 * dx0
32+
val re1 = x1 * dy1 - y1 * dx1
33+
val re2 = x2 * dy2 - y2 * dx2
34+
35+
val eWidth = signedBitLength(2 * (VgaTiming.width - 1) * (VgaTiming.height - 1))
36+
val e0 = RegInit(re0.S(eWidth.W))
37+
val e1 = RegInit(re1.S(eWidth.W))
38+
val e2 = RegInit(re2.S(eWidth.W))
39+
1440
val col = RegInit(0.U(log2Up(Tile.nrCols).W))
1541
val row = RegInit(0.U(unsignedBitLength(Tile.nrRows).W))
1642
when (RegNext(io.fbId) =/= io.fbId) {
43+
e0 := re0.S
44+
e1 := re1.S
45+
e2 := re2.S
1746
col := 0.U
1847
row := 0.U
1948
}
@@ -22,17 +51,29 @@ class Graphics extends Module {
2251
val valid = row < Tile.nrRows.U
2352
tileBuffer.io.inReq.valid := valid
2453
when (valid && tileBuffer.io.inReq.ready) {
54+
e0 := e0 - (Tile.size * dy0).S
55+
e1 := e1 - (Tile.size * dy1).S
56+
e2 := e2 - (Tile.size * dy2).S
2557
col := col + 1.U
2658
when (col === (Tile.nrCols - 1).U) {
59+
e0 := e0 + (Tile.size * ((Tile.nrCols - 1) * dy0 + dx0)).S
60+
e1 := e1 + (Tile.size * ((Tile.nrCols - 1) * dy1 + dx1)).S
61+
e2 := e2 + (Tile.size * ((Tile.nrCols - 1) * dy2 + dx2)).S
2762
col := 0.U
2863
row := row + 1.U
2964
}
3065
}
66+
67+
3168
for (i <- 0 until Tile.size) {
3269
for (j <- 0 until Tile.size) {
33-
tileBuffer.io.inReq.bits(i)(j).r := col << 2.U
34-
tileBuffer.io.inReq.bits(i)(j).g := row << 2.U
35-
tileBuffer.io.inReq.bits(i)(j).b := "hff".U
70+
val pe0 = e0 + (i * dx0 - j * dy0).S
71+
val pe1 = e1 + (i * dx1 - j * dy1).S
72+
val pe2 = e2 + (i * dx2 - j * dy2).S
73+
val visible = pe0 < 0.S && pe1 < 0.S && pe2 < 0.S
74+
tileBuffer.io.inReq.bits(i)(j).r := Mux(visible, 255.U, 0.U)
75+
tileBuffer.io.inReq.bits(i)(j).g := Mux(visible, 255.U, 0.U)
76+
tileBuffer.io.inReq.bits(i)(j).b := Mux(visible, 255.U, 0.U)
3677
}
3778
}
3879

‎src/main/scala/graphics/TileBuffer.scala

+5-9
Original file line numberDiff line numberDiff line change
@@ -48,26 +48,22 @@ class TileBuffer extends Module {
4848
val idx = RegInit(0.U(log2Up(Tile.size / Fb.nrBanks).W))
4949
val nextFron = WireDefault(fron)
5050
val nextCol = WireDefault(col)
51-
val nextRow = WireDefault(row)
52-
val nextIdx = WireDefault(idx)
5351
val writing = size >= Tile.nrCols.U
5452
io.outReq.valid := writing
5553
val pix = Wire(Vec(Fb.nrBanks, FbRGB()))
5654
for (i <- 0 until Fb.nrBanks) {
57-
pix(i) := buf.read(nextFron + nextCol)(nextRow)(nextIdx << log2Up(Fb.nrBanks) | i.U)
55+
pix(i) := buf.read(nextFron + nextCol)(row)(idx << log2Up(Fb.nrBanks) | i.U)
5856
}
5957
io.outReq.bits.pix := pix
6058
when (writing && io.outReq.ready) {
61-
nextIdx := idx + 1.U
62-
idx := nextIdx
59+
idx := idx + 1.U
6360
when (idx === (Tile.size / Fb.nrBanks - 1).U) {
64-
nextIdx := 0.U
61+
idx := 0.U
6562
nextCol := col + 1.U
66-
col := nextCol
63+
col := nextCol
6764
when (col === (Tile.nrCols - 1).U) {
6865
nextCol := 0.U
69-
nextRow := row + 1.U
70-
row := nextRow
66+
row := row + 1.U
7167
when (row === (Tile.size - 1).U) {
7268
row := 0.U
7369
nextFron := fron + Tile.nrCols.U

‎vivado/bd/vram/ip/vram_auto_cc_0/vram_auto_cc_0.xci

+378
Large diffs are not rendered by default.

‎vivado/bd/vram/ip/vram_auto_cc_1/vram_auto_cc_1.xci

+286
Large diffs are not rendered by default.

‎vivado/bd/vram/ip/vram_auto_cc_2/vram_auto_cc_2.xci

+298
Large diffs are not rendered by default.

‎vivado/bd/vram/ip/vram_clk_wiz_0_0/vram_clk_wiz_0_0.xci

+7-7
Original file line numberDiff line numberDiff line change
@@ -619,10 +619,10 @@
619619
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
620620
"mode": "slave",
621621
"parameters": {
622-
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
622+
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
623623
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
624624
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
625-
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
625+
"CLK_DOMAIN": [ { "value": "vram_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
626626
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
627627
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
628628
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
@@ -638,9 +638,9 @@
638638
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
639639
"mode": "master",
640640
"parameters": {
641-
"FREQ_HZ": [ { "value": "200000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
641+
"FREQ_HZ": [ { "value": "200000000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
642642
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
643-
"PHASE": [ { "value": "0.0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
643+
"PHASE": [ { "value": "0.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
644644
"CLK_DOMAIN": [ { "value": "vram_clk_wiz_0_0_clk_ref", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
645645
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
646646
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
@@ -656,10 +656,10 @@
656656
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
657657
"mode": "master",
658658
"parameters": {
659-
"FREQ_HZ": [ { "value": "166666666", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
659+
"FREQ_HZ": [ { "value": "166666666", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
660660
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
661-
"PHASE": [ { "value": "0.0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
662-
"CLK_DOMAIN": [ { "value": "vram_clk_wiz_0_0_clk_ref", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
661+
"PHASE": [ { "value": "0.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
662+
"CLK_DOMAIN": [ { "value": "vram_clk_wiz_0_0_clk_ref", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
663663
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
664664
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
665665
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],

‎vivado/bd/vram/ip/vram_mig_7series_0_0/vram_mig_7series_0_0.xci

+1-1
Original file line numberDiff line numberDiff line change
@@ -1183,7 +1183,7 @@
11831183
"OUTPUTDIR": [ { "value": "." } ],
11841184
"SELECTEDSIMMODEL": [ { "value": "" } ],
11851185
"SHAREDDIR": [ { "value": "../../ipshared" } ],
1186-
"SWVERSION": [ { "value": "2023.1" } ],
1186+
"SWVERSION": [ { "value": "2023.2" } ],
11871187
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
11881188
}
11891189
},

‎vivado/bd/vram/ip/vram_proc_sys_reset_0_0/vram_proc_sys_reset_0_0.xci

+2-2
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@
7878
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
7979
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
8080
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
81-
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
81+
"CLK_DOMAIN": [ { "value": "vram_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
8282
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
8383
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
8484
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
@@ -93,7 +93,7 @@
9393
"mode": "slave",
9494
"parameters": {
9595
"BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
96-
"POLARITY": [ { "value": "ACTIVE_LOW", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
96+
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
9797
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
9898
},
9999
"port_maps": {

‎vivado/bd/vram/ip/vram_proc_sys_reset_1_0/vram_proc_sys_reset_1_0.xci

+3-3
Original file line numberDiff line numberDiff line change
@@ -77,8 +77,8 @@
7777
"ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
7878
"FREQ_HZ": [ { "value": "83333333", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
7979
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
80-
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
81-
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
80+
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
81+
"CLK_DOMAIN": [ { "value": "vram_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
8282
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
8383
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
8484
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
@@ -93,7 +93,7 @@
9393
"mode": "slave",
9494
"parameters": {
9595
"BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
96-
"POLARITY": [ { "value": "ACTIVE_LOW", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
96+
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
9797
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
9898
},
9999
"port_maps": {

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