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alanjian85alanjian85
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Upgrade Vivado IPs
1 parent 4cab7eb commit 750fdef

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11 files changed

+190
-1415
lines changed

11 files changed

+190
-1415
lines changed

‎vivado/bd/vram/ip/vram_auto_cc_0/vram_auto_cc_0.xci

-378
This file was deleted.

‎vivado/bd/vram/ip/vram_auto_cc_1/vram_auto_cc_1.xci

-286
This file was deleted.

‎vivado/bd/vram/ip/vram_auto_cc_2/vram_auto_cc_2.xci

-298
This file was deleted.

‎vivado/bd/vram/ip/vram_axi_interconnect_0_0/vram_axi_interconnect_0_0.xci

+3-3
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
"xci_name": "vram_axi_interconnect_0_0",
55
"cell_name": "axi_interconnect_0",
66
"component_reference": "xilinx.com:ip:axi_interconnect:2.1",
7-
"ip_revision": "29",
7+
"ip_revision": "30",
88
"gen_directory": ".",
99
"parameters": {
1010
"component_parameters": {
@@ -339,12 +339,12 @@
339339
},
340340
"runtime_parameters": {
341341
"IPCONTEXT": [ { "value": "IP_Integrator_AppCore" } ],
342-
"IPREVISION": [ { "value": "29" } ],
342+
"IPREVISION": [ { "value": "30" } ],
343343
"MANAGED": [ { "value": "TRUE" } ],
344344
"OUTPUTDIR": [ { "value": "." } ],
345345
"SELECTEDSIMMODEL": [ { "value": "" } ],
346346
"SHAREDDIR": [ { "value": "../../ipshared" } ],
347-
"SWVERSION": [ { "value": "2023.1" } ],
347+
"SWVERSION": [ { "value": "2023.2" } ],
348348
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
349349
}
350350
}

‎vivado/bd/vram/ip/vram_clk_wiz_0_0/vram_clk_wiz_0_0.xci

+10-10
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
"xci_name": "vram_clk_wiz_0_0",
55
"cell_name": "clk_wiz_0",
66
"component_reference": "xilinx.com:ip:clk_wiz:6.0",
7-
"ip_revision": "12",
7+
"ip_revision": "13",
88
"gen_directory": ".",
99
"parameters": {
1010
"component_parameters": {
@@ -598,12 +598,12 @@
598598
},
599599
"runtime_parameters": {
600600
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
601-
"IPREVISION": [ { "value": "12" } ],
601+
"IPREVISION": [ { "value": "13" } ],
602602
"MANAGED": [ { "value": "TRUE" } ],
603603
"OUTPUTDIR": [ { "value": "." } ],
604604
"SELECTEDSIMMODEL": [ { "value": "" } ],
605605
"SHAREDDIR": [ { "value": "../../ipshared" } ],
606-
"SWVERSION": [ { "value": "2023.1" } ],
606+
"SWVERSION": [ { "value": "2023.2" } ],
607607
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
608608
}
609609
},
@@ -619,10 +619,10 @@
619619
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
620620
"mode": "slave",
621621
"parameters": {
622-
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
622+
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
623623
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
624624
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
625-
"CLK_DOMAIN": [ { "value": "vram_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
625+
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
626626
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
627627
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
628628
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
@@ -638,9 +638,9 @@
638638
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
639639
"mode": "master",
640640
"parameters": {
641-
"FREQ_HZ": [ { "value": "200000000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
641+
"FREQ_HZ": [ { "value": "200000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
642642
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
643-
"PHASE": [ { "value": "0.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
643+
"PHASE": [ { "value": "0.0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
644644
"CLK_DOMAIN": [ { "value": "vram_clk_wiz_0_0_clk_ref", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
645645
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
646646
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
@@ -656,10 +656,10 @@
656656
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
657657
"mode": "master",
658658
"parameters": {
659-
"FREQ_HZ": [ { "value": "166666666", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
659+
"FREQ_HZ": [ { "value": "166666666", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
660660
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
661-
"PHASE": [ { "value": "0.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
662-
"CLK_DOMAIN": [ { "value": "vram_clk_wiz_0_0_clk_ref", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
661+
"PHASE": [ { "value": "0.0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
662+
"CLK_DOMAIN": [ { "value": "vram_clk_wiz_0_0_clk_ref", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
663663
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
664664
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
665665
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],

‎vivado/bd/vram/ip/vram_proc_sys_reset_0_0/vram_proc_sys_reset_0_0.xci

+5-5
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
"xci_name": "vram_proc_sys_reset_0_0",
55
"cell_name": "proc_sys_reset_0",
66
"component_reference": "xilinx.com:ip:proc_sys_reset:5.0",
7-
"ip_revision": "13",
7+
"ip_revision": "14",
88
"gen_directory": ".",
99
"parameters": {
1010
"component_parameters": {
@@ -46,12 +46,12 @@
4646
},
4747
"runtime_parameters": {
4848
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
49-
"IPREVISION": [ { "value": "13" } ],
49+
"IPREVISION": [ { "value": "14" } ],
5050
"MANAGED": [ { "value": "TRUE" } ],
5151
"OUTPUTDIR": [ { "value": "." } ],
5252
"SELECTEDSIMMODEL": [ { "value": "" } ],
5353
"SHAREDDIR": [ { "value": "../../ipshared" } ],
54-
"SWVERSION": [ { "value": "2023.1" } ],
54+
"SWVERSION": [ { "value": "2023.2" } ],
5555
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
5656
}
5757
},
@@ -78,7 +78,7 @@
7878
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
7979
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
8080
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
81-
"CLK_DOMAIN": [ { "value": "vram_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
81+
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
8282
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
8383
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
8484
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
@@ -93,7 +93,7 @@
9393
"mode": "slave",
9494
"parameters": {
9595
"BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
96-
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
96+
"POLARITY": [ { "value": "ACTIVE_LOW", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
9797
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
9898
},
9999
"port_maps": {

‎vivado/bd/vram/ip/vram_proc_sys_reset_1_0/vram_proc_sys_reset_1_0.xci

+6-6
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
"xci_name": "vram_proc_sys_reset_1_0",
55
"cell_name": "proc_sys_reset_1",
66
"component_reference": "xilinx.com:ip:proc_sys_reset:5.0",
7-
"ip_revision": "13",
7+
"ip_revision": "14",
88
"gen_directory": ".",
99
"parameters": {
1010
"component_parameters": {
@@ -46,12 +46,12 @@
4646
},
4747
"runtime_parameters": {
4848
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
49-
"IPREVISION": [ { "value": "13" } ],
49+
"IPREVISION": [ { "value": "14" } ],
5050
"MANAGED": [ { "value": "TRUE" } ],
5151
"OUTPUTDIR": [ { "value": "." } ],
5252
"SELECTEDSIMMODEL": [ { "value": "" } ],
5353
"SHAREDDIR": [ { "value": "../../ipshared" } ],
54-
"SWVERSION": [ { "value": "2023.1" } ],
54+
"SWVERSION": [ { "value": "2023.2" } ],
5555
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
5656
}
5757
},
@@ -77,8 +77,8 @@
7777
"ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
7878
"FREQ_HZ": [ { "value": "83333333", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
7979
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
80-
"PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
81-
"CLK_DOMAIN": [ { "value": "vram_mig_7series_0_0_ui_clk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
80+
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
81+
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
8282
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
8383
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
8484
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
@@ -93,7 +93,7 @@
9393
"mode": "slave",
9494
"parameters": {
9595
"BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
96-
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
96+
"POLARITY": [ { "value": "ACTIVE_LOW", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
9797
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
9898
},
9999
"port_maps": {

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