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1 parent 0ea9723 commit a3c2e45Copy full SHA for a3c2e45
src/main/scala/graphics/TileWriter.scala
@@ -35,12 +35,14 @@ class TileWriter extends Module {
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val size = RegInit(0.U(unsignedBitLength(buf.length).W))
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val nextRear = Mux(rear =/= (buf.length - 1).U, rear + 1.U, 0.U)
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+ val nextSize = WireDefault(size)
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val full = nextRear === fron
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io.inReq.ready := !full
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when (!full && io.inReq.valid) {
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buf.write(rear, io.inReq.bits)
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rear := nextRear
- size := size + 1.U
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+ nextSize := size + 1.U
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+ size := nextSize
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}
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val col = RegInit(0.U(log2Up(Tile.nrCols).W))
@@ -72,7 +74,7 @@ class TileWriter extends Module {
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when (fron === (buf.length - Tile.nrCols).U) {
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nextFron := 0.U
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- size := size - Tile.nrCols.U
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+ size := nextSize - Tile.nrCols.U
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