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1 parent 7148dcd commit 0ea9723Copy full SHA for 0ea9723
src/main/scala/graphics/TileWriter.scala
@@ -51,8 +51,9 @@ class TileWriter extends Module {
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val writing = size >= Tile.nrCols.U
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io.outReq.valid := writing
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val pix = Wire(Vec(Fb.nrBanks, FbRGB()))
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+ val tile = buf.read(nextFron + nextCol)
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for (i <- 0 until Fb.nrBanks) {
- pix(i) := buf.read(nextFron + nextCol)(row)(idx << log2Up(Fb.nrBanks) | i.U)
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+ pix(i) := tile(row)(idx << log2Up(Fb.nrBanks) | i.U)
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}
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io.outReq.bits.pix := pix
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when (writing && io.outReq.ready) {
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