Implement TileBuffer

Author: alanjian85

.gitignore

@@ -1,7 +1,8 @@
 .bloop
 .metals
 .vscode
+.bsp
 generated
 project
 target
-verilator/obj_dir
+verilator/obj_dir

src/main/scala/core/Fb.scala

@@ -172,7 +172,6 @@ class FbWriter extends Module {
     val vram = new WrAxi(Vram.addrWidth, Vram.dataWidth)
     val fbId = Input(UInt(Fb.idWidth.W))
     val req  = Flipped(Irrevocable(new FbWrReq))
-    val idx  = Output(UInt(log2Up(Fb.nrIndices).W))
     val done = Output(Bool())
   })
 
@@ -208,15 +207,12 @@ class FbWriter extends Module {
   io.vram.data.bits.strb := Fill(Vram.dataBytes, 1.U)
   io.vram.data.bits.last := last
   io.req.ready := io.vram.data.ready
-  io.idx := idx
   when (io.req.valid && io.vram.data.ready) {
-    val nextIdx = WireDefault(idx + 1.U)
+    idx := idx + 1.U
     when (last) {
-      nextIdx   := 0.U
+      idx       := 0.U
       addrBegan := false.B
     }
-    idx    := nextIdx
-    io.idx := nextIdx
   }
 
   io.vram.resp.ready := true.B

src/main/scala/display/Display.scala

@@ -16,7 +16,7 @@ class Display extends Module {
   vgaSignal.io.currPos := vgaPos
   io.vga := vgaSignal.io.vga
 
-  val buffer    = SyncReadMem(Fb.nrIndices, Vec(Fb.nrBanks, VgaRGB()))
+  val buf       = SyncReadMem(Fb.nrIndices, Vec(Fb.nrBanks, VgaRGB()))
   val fbReader  = Module(new FbReader)
   val rdReqLine = RegInit(0.U(log2Up(Fb.height).W))
   io.vram <> fbReader.io.vram
@@ -36,9 +36,9 @@ class Display extends Module {
       pix(i).g := dither(VgaRGB.gWidth, fbReader.io.res.bits.pix(i).g, rdReqLine, i)
       pix(i).b := dither(VgaRGB.bWidth, fbReader.io.res.bits.pix(i).b, rdReqLine, i)
     }
-    buffer.write(fbReader.io.res.bits.idx, pix)
+    buf.write(fbReader.io.res.bits.idx, pix)
   }
 
-  val pixBanks = buffer.read(vgaSignal.io.nextPos.x >> log2Up(Fb.nrBanks))
+  val pixBanks = buf.read(vgaSignal.io.nextPos.x >> log2Up(Fb.nrBanks))
   vgaSignal.io.pix := pixBanks(vgaPos.x(log2Up(Fb.nrBanks) - 1, 0))
 }

src/main/scala/display/Dithering.scala

@@ -25,7 +25,6 @@ object dither {
           bayer(i)(j) := c.U
         }
       }
-
       val sum = x +& bayer(row)(col)
       res := sum >> dstWidth
       when (sum(x.getWidth)) {

src/main/scala/graphics/Graphics.scala

@@ -11,24 +11,34 @@ class Graphics extends Module {
     val done = Output(Bool())
   })
 
-  val line = RegInit(0.U(unsignedBitLength(Fb.height).W))
-  val done = line === Fb.height.U
+  val col = RegInit(0.U(log2Up(Tile.nrCols).W))
+  val row = RegInit(0.U(unsignedBitLength(Tile.nrRows).W))
+  when (RegNext(io.fbId) =/= io.fbId) {
+    col := 0.U
+    row := 0.U
+  }
+
+  val tileBuffer = Module(new TileBuffer)
+  val valid = row < Tile.nrRows.U
+  tileBuffer.io.inReq.valid := valid
+  when (valid && tileBuffer.io.inReq.ready) {
+    col := col + 1.U
+    when (col === (Tile.nrCols - 1).U) {
+      col := 0.U
+      row := row + 1.U
+    }
+  }
+  for (i <- 0 until Tile.size) {
+    for (j <- 0 until Tile.size) {
+      tileBuffer.io.inReq.bits(i)(j).r := col << 2.U
+      tileBuffer.io.inReq.bits(i)(j).g := row << 2.U
+      tileBuffer.io.inReq.bits(i)(j).b := "hff".U
+    }
+  }
+
   val fbWriter = Module(new FbWriter)
   io.vram <> fbWriter.io.vram
   fbWriter.io.fbId := io.fbId
-  fbWriter.io.req.valid := !done
-  val color = Wire(FbRGB())
-  color.r := RegNext((fbWriter.io.idx >> 4) ## 0.U(4.W))
-  color.g := color.r
-  color.b := color.r
-  fbWriter.io.req.bits.pix := VecInit(Seq.fill(Fb.nrBanks)(
-    color.map(color => Mux(line < (Fb.height / 2).U, color, gammaCorrect(color)))
-  ))
-  when (!done && fbWriter.io.req.ready && fbWriter.io.idx === 0.U) {
-    line := line + 1.U
-  }
-  when (RegNext(io.fbId) =/= io.fbId) {
-    line := 0.U
-  }
-  io.done := fbWriter.io.done
+  fbWriter.io.req <> tileBuffer.io.outReq
+  io.done := !valid && fbWriter.io.done
 }

src/main/scala/graphics/TileBuffer.scala

@@ -5,19 +5,22 @@ import chisel3._
 import chisel3.util._
 
 object Tile {
-  val width = 32
+  val size = 16
 
-  val nrRows = (Fb.width  + width - 1) / width * width
-  val nrCols = (Fb.height + width - 1) / width * width
+  val nrCols = (Fb.width  + size - 1) / size
+  val nrRows = (Fb.height + size - 1) / size
+
+  val width  = nrCols * size
+  val height = nrRows * size
+
+  def apply() = new Tile
 }
 
 class Tile extends Bundle {
-  val elem = Vec(Tile.width, Vec(Tile.width, FbRGB()))
+  val elem = Vec(Tile.size, Vec(Tile.size, FbRGB()))
 
-  def apply(i: Int,  j: Int)  = elem(i)(j)
-  def apply(i: Int,  j: UInt) = elem(i)(j)
-  def apply(i: UInt, j: Int)  = elem(i)(j)
-  def apply(i: UInt, j: UInt) = elem(i)(j)
+  def apply(idx: Int)  = elem(idx)
+  def apply(idx: UInt) = elem(idx)
 }
 
 class TileBuffer extends Module {
@@ -26,5 +29,55 @@ class TileBuffer extends Module {
     val outReq = Irrevocable(new FbWrReq)
   })
 
+  val buf = SyncReadMem(2 * Tile.nrCols, Tile())
+  val fron = RegInit(0.U(log2Up(buf.length).W))
+  val rear = RegInit(0.U(log2Up(buf.length).W))
+  val size = RegInit(0.U(unsignedBitLength(buf.length).W))
+
+  val nextRear = Mux(rear =/= (buf.length - 1).U, rear + 1.U, 0.U)
+  val full     = nextRear === fron
+  io.inReq.ready := !full
+  when (!full && io.inReq.valid) {
+    buf.write(rear, io.inReq.bits)
+    rear := nextRear
+    size := size + 1.U
+  }
 
+  val col  = RegInit(0.U(log2Up(Tile.nrCols).W))
+  val row  = RegInit(0.U(log2Up(Tile.size).W))
+  val idx  = RegInit(0.U(log2Up(Tile.size / Fb.nrBanks).W))
+  val nextFron = WireDefault(fron)
+  val nextCol  = WireDefault(col)
+  val nextRow  = WireDefault(row)
+  val nextIdx  = WireDefault(idx)
+  val writing  = size >= Tile.nrCols.U
+  io.outReq.valid := writing
+  val pix = Wire(Vec(Fb.nrBanks, FbRGB()))
+  for (i <- 0 until Fb.nrBanks) {
+    pix(i) := buf.read(nextFron + nextCol)(nextRow)(nextIdx << log2Up(Fb.nrBanks) | i.U)
+  }
+  io.outReq.bits.pix := pix
+  when (writing && io.outReq.ready) {
+    nextIdx := idx + 1.U
+    idx     := nextIdx
+    when (idx === (Tile.size / Fb.nrBanks - 1).U) {
+      nextIdx := 0.U
+      nextCol := col + 1.U
+      col := nextCol
+      when (col === (Tile.nrCols - 1).U) {
+        nextCol := 0.U
+        nextRow := row + 1.U
+        row     := nextRow
+        when (row === (Tile.size - 1).U) {
+          row      := 0.U
+          nextFron := fron + Tile.nrCols.U
+          fron     := nextFron
+          when (fron === (buf.length - Tile.nrCols).U) {
+            nextFron := 0.U
+          }
+          size := size - Tile.nrCols.U
+        }
+      }
+    }
+  }
 }