@@ -24,13 +24,13 @@ class Graphics extends Module {
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val dx1 = x2 - x1
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val dx2 = x0 - x2
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- val dy0 = y1 - y0
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- val dy1 = y2 - y1
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- val dy2 = y0 - y2
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+ val dy0 = y0 - y1
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+ val dy1 = y1 - y2
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+ val dy2 = y2 - y0
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- val re0 = x0 * dy0 - y0 * dx0
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- val re1 = x1 * dy1 - y1 * dx1
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- val re2 = x2 * dy2 - y2 * dx2
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+ val re0 = dx0 * y0 + dy0 * x0
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+ val re1 = dx1 * y1 + dy1 * x1
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+ val re2 = dx2 * y2 + dy2 * x2
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val eWidth = signedBitLength(2 * (VgaTiming .width - 1 ) * (VgaTiming .height - 1 ))
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val e0 = RegInit (re0.S (eWidth.W ))
@@ -51,14 +51,14 @@ class Graphics extends Module {
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val valid = row < Tile .nrRows.U
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tileBuffer.io.inReq.valid := valid
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when (valid && tileBuffer.io.inReq.ready) {
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- e0 := e0 - (Tile .size * dy0 ).S
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- e1 := e1 - (Tile .size * dy1 ).S
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- e2 := e2 - (Tile .size * dy2 ).S
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+ e0 := e0 - (dy0 * Tile .size ).S
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+ e1 := e1 - (dy1 * Tile .size ).S
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+ e2 := e2 - (dy2 * Tile .size ).S
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col := col + 1 .U
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when (col === (Tile .nrCols - 1 ).U ) {
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- e0 := e0 + (Tile .size * (( Tile .nrCols - 1 ) * dy0 + dx0)).S
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- e1 := e1 + (Tile .size * (( Tile .nrCols - 1 ) * dy1 + dx1)).S
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- e2 := e2 + (Tile .size * (( Tile .nrCols - 1 ) * dy2 + dx2)).S
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+ e0 := e0 + ((dy0 * (Tile .nrCols - 1 ) - dx0) * Tile .size ).S
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+ e1 := e1 + ((dy1 * (Tile .nrCols - 1 ) - dx1) * Tile .size ).S
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+ e2 := e2 + ((dy2 * (Tile .nrCols - 1 ) - dx2) * Tile .size ).S
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col := 0 .U
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row := row + 1 .U
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}
@@ -67,10 +67,10 @@ class Graphics extends Module {
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for (i <- 0 until Tile .size) {
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for (j <- 0 until Tile .size) {
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- val pe0 = e0 + (i * dx0 - j * dy0 ).S
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- val pe1 = e1 + (i * dx1 - j * dy1 ).S
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- val pe2 = e2 + (i * dx2 - j * dy2 ).S
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- val visible = pe0 < 0 .S && pe1 < 0 .S && pe2 < 0 .S
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+ val pe0 = e0 - (dx0 * i + dy0 * j ).S
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+ val pe1 = e1 - (dx1 * i + dy1 * j ).S
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+ val pe2 = e2 - (dx2 * i + dy2 * j ).S
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+ val visible = pe0 >= 0 .S && pe1 >= 0 .S && pe2 >= 0 .S
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tileBuffer.io.inReq.bits(i)(j).r := Mux (visible, 255 .U , 0 .U )
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tileBuffer.io.inReq.bits(i)(j).g := Mux (visible, 255 .U , 0 .U )
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tileBuffer.io.inReq.bits(i)(j).b := Mux (visible, 255 .U , 0 .U )
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