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alanjian85 committed Dec 21, 2023
1 parent c68be01 commit 16ad341
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Showing 11 changed files with 92 additions and 319 deletions.
4 changes: 2 additions & 2 deletions src/main/scala/core/Fb.scala
Original file line number Diff line number Diff line change
Expand Up @@ -47,7 +47,7 @@ class vram extends BlackBox {

class Vram extends Module {
val io = IO(new Bundle {
val axiGraphics = Flipped(new WrAxi(Vram.addrWidth, Vram.dataWidth))
val axiGraphics = new WrAxiExtUpper(Vram.addrWidth, Vram.dataWidth)
val aclkGraphics = Input(Clock())
val arstnGraphics = Input(Reset())

Expand All @@ -62,7 +62,7 @@ class Vram extends Module {
vram.io.clk := clock.asBool
vram.io.reset := reset.asBool

vram.io.graphics_axi.connect(io.axiGraphics)
io.axiGraphics.connect(vram.io.graphics_axi)
vram.io.graphics_aclk := io.aclkGraphics.asBool
vram.io.graphics_aresetn := io.arstnGraphics.asBool

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8 changes: 4 additions & 4 deletions src/main/scala/core/Trinity.scala
Original file line number Diff line number Diff line change
Expand Up @@ -36,10 +36,10 @@ class Trinity extends Module {
vram.io.aclkGraphics := clkWiz.io.clkGraphics
vram.io.arstnGraphics := graphicsSysRst.io.periArstn
withClockAndReset(clkWiz.io.clkGraphics, graphicsSysRst.io.periRst) {
val graphics = Module(new Graphics)
vram.io.axiGraphics <> graphics.io.vram
graphics.io.fbId := RegNext(RegNext(fbSwapper.io.graphicsFbId))
graphicsDone := RegNext(graphics.io.done)
val renderer = Module(new Renderer)
vram.io.axiGraphics <> renderer.io.vram
renderer.io.fbId := RegNext(RegNext(fbSwapper.io.graphicsFbId))
graphicsDone := RegNext(renderer.io.done)
}
}

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20 changes: 0 additions & 20 deletions src/main/scala/graphics/GammaCorrection.scala

This file was deleted.

203 changes: 0 additions & 203 deletions src/main/scala/graphics/Graphics.scala

This file was deleted.

82 changes: 0 additions & 82 deletions src/main/scala/graphics/TileWriter.scala

This file was deleted.

26 changes: 26 additions & 0 deletions src/main/scala/renderer/Renderer.scala
Original file line number Diff line number Diff line change
@@ -0,0 +1,26 @@
import chisel3._

class renderer extends BlackBox {
val io = IO(new Bundle {
val ap_clk = Input(Bool())
val ap_rst_n = Input(Bool())
val fb_id = Input(UInt(Fb.idWidth.W))
val m_axi_vram = Flipped(new WrAxiExtUpper(64, 128))
val done = Output(Bool())
})
}

class Renderer extends Module {
val io = IO(new Bundle {
val fbId = Input(UInt(Fb.idWidth.W))
val vram = Flipped(new WrAxiExtUpper(64, 128))
val done = Output(Bool())
})

val renderer = Module(new renderer)
renderer.io.ap_clk := clock.asBool
renderer.io.ap_rst_n := !reset.asBool
renderer.io.fb_id := io.fbId
renderer.io.m_axi_vram <> io.vram
io.done := renderer.io.done
}
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