Mon Dec 9 10:02:47 PM PST 2024

rapidstream-org · Dec 10, 2024 · eeb80a5 · eeb80a5
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commit eeb80a5
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Showing 3 changed files with 45 additions and 2 deletions.
diff --git a/getting_started/tapa_source/Makefile b/getting_started/tapa_source/Makefile
@@ -25,6 +25,7 @@ RS_TARGET        := $(TEMP_DIR)/dse/candidate_0/exported/VecAdd.xo
 TIMING_RPT       := impl_1_hw_bb_locked_timing_summary_routed.rpt
 SUCCESS          := "Build Successful"
 SLACK_GETTER     := $(ROOT_DIR)/common/util/get_slack.py
+SLOT_GETTER      := $(ROOT_DIR)/common/util/get_slot.py
 BUILD_LOG        := $(TEMP_DIR)/build.json
 RSXX             := rapidstream
 RSPATH           := $(CURDIR)
@@ -44,6 +45,7 @@ $(RS_KERNEL_XCLBIN):$(KERNEL_XO) $(DEVICE_CONFIG) $(AB_CONFIG)
     --tapa-xo-path $< \
     --device-config $(DEVICE_CONFIG) \
     --floorplan-config $(AB_CONFIG) \
+	--run-impl \
     --implementation-config $(IMPL_CONFIG) \
     --connectivity-ini $(LINK_CONFIG)
 
@@ -84,6 +86,8 @@ $(TEMP_DIR)/main.exe: $(SRC_DIR)/main.cpp $(SRC_DIR)/VecAdd.cpp
 	mkdir -p $(TEMP_DIR)
 	cd $(TEMP_DIR) && tapa g++ $^ $(INCLUDE) -o $@ -O2
 
+check_floorplan:
+	$(RSPYTHON) $(SLOT_GETTER) -i $(TEMP_DIR) -o $(TEMP_DIR)
 
 show_groups:
 	@echo $(RS_KERNEL_XCLBIN)

diff --git a/getting_started/tapa_source/README.md b/getting_started/tapa_source/README.md
@@ -122,6 +122,7 @@ You can run the command below or execute `make all` supported by our [Makefile](
 rapidstream-tapaopt --work-dir build/run_u55c.py \
                     --tapa-xo-path ./VecAdd.xo \
                     --device-config build/run_u55c.py/device.json \
+                    --run-impl \
                     --floorplan-config ../../design/config/run_u55c.py/ab_config.json \
                     --implementation-config ../../ design/config/run_u55c.py/impl_config.json \
                     --connectivity-ini ../../design/config/run_u55c.py/link_config.ini
@@ -135,6 +136,44 @@ find ./build/run_u55c.py/ -name *.xo
 
 If everything is successful, you should at least get one optimized `.xo` file located in `build/run_u55c.py/dse/solution_0/updated.xo`.
 
+Since we enable '--run-impl' option, rapidstream will launch Vitis to generate the `.xclbin` file for the optimized `.xo` file.
+You can find the optimized `.xclbin` file by running the following command:
+
+```bash
+find ./build -name *.xclbin.info
+```
+
+### Step 6: Check the Real Floorplan Report
+Since assign the cell "add_kernel" to "SLOT_X1Y1" in the configure file ([floorplan_config.json](design/config/run_u55c.py/floorplan_config.json)),
+we can check the real floorplan report by running the following command or `make check_floorplan`:
+
+```bash
+rapidstream ../../common/util/get_slot.py \
+  -i build/run_u55c.py \
+  -o  build/run_u55c.py
+```
+
+You can open the `build/run_u55c.py/floorplan_solution_<N>.csv" to check the real floorplan report. I may find more than one .csv files depending on the number of solutions.
+
+| Module Name                      | Group Type     |
+|:--------------------------------:|:--------------:|
+| VecAdd                           | grouped_module |
+| __rs_VecAdd_aux                  |  aux_module    |
+| ...                              | verilog_module |
+
+
+|name           |floorplan              |ff     |lut     |bram_18k |dsp  |uram |unpipelinable|
+|:-------------:|:----------------------:|:----:|:------:|:-------:|:---:|:---:|:-----------:|
+add_kernel_0    | SLOT_X1Y1_TO_SLOT_X1Y1 | 54   | 65     | 0       | 0   | 0   |             |
+control_s_axi_U | SLOT_X1Y0_TO_SLOT_X1Y0 | 245  | 223    | 0       | 0   | 0   |             |
+read_mem_0      | SLOT_X1Y0_TO_SLOT_X1Y0 | 790  | 546    | 1       | 0   | 0   |             |
+read_mem_1      | SLOT_X1Y0_TO_SLOT_X1Y0 | 790  | 546    | 1       | 0   | 0   |             |
+stream_in1      | SLOT_X1Y0_TO_SLOT_X1Y0 | 10   | 53     | 0       | 0   | 0   |             |
+stream_in2      | SLOT_X1Y1_TO_SLOT_X1Y1 | 10   | 53     | 0       | 0   | 0   |             |
+stream_out      | SLOT_X1Y0_TO_SLOT_X1Y0 | 10   | 53     | 0       | 0   | 0   |             |
+write_mem_0     | SLOT_X1Y0_TO_SLOT_X1Y0 | 1024 | 768    | 1       | 0   | 0   |             |
+__tapa_fsm_unit_write_mem_0|SLOT_X1Y0_TO_SLOT_X1Y0|0|0|0|0|0|non_pipeline|
+
 ### Step 7: Check the Group Module Report
 
 
@@ -163,7 +202,7 @@ The module types for your design can be found in `build/module_types.csv`. Below
 | ...                              | verilog_module |
 
 
-### Step 8: Use Vitis --link with the Optimized `.xo` File
+### Step 8: Use Vitis --link with the Optimized `.xo` File (optional)
 
 With the optimized `.xo` file generated, you can use `v++ -link` to generate the `.xclbin` file. Run the following command or run `make`:
 

diff --git a/getting_started/tapa_source/design/config/run_u55c.py/floorplan_config.json b/getting_started/tapa_source/design/config/run_u55c.py/floorplan_config.json
@@ -1,5 +1,5 @@
 {
-    "cells_pre_assignments": {
+    "cell_pre_assignments": {
         ".*add_kernel.*": "SLOT_X1Y1_TO_SLOT_X1Y1"
     },
     "dse_range_max": 0.8,