pulp-platform · smanoni · Mar 11, 2026 · Mar 11, 2026 · Mar 12, 2026 · Apr 8, 2026
diff --git a/.gitmodules b/.gitmodules
@@ -69,7 +69,8 @@
 	url = https://github.com/pulp-platform/icache-intc.git
 [submodule "hw/ips/jtag_pulp"]
 	path = hw/ips/jtag_pulp
-	url = https://github.com/pulp-platform/jtag_pulp.git
+	url = git@github.com:smanoni/jtag_pulp.git
+	branch = sm/lint
 [submodule "hw/ips/l2_tcdm_hybrid_interco"]
 	path = hw/ips/l2_tcdm_hybrid_interco
 	url = https://github.com/pulp-platform/L2_tcdm_hybrid_interco.git
@@ -99,7 +100,8 @@
 	url = git@github.com:pulp-platform/tech_cells_generic.git
 [submodule "hw/ips/timer_unit"]
 	path = hw/ips/timer_unit
-	url = https://github.com/pulp-platform/timer_unit.git
+	url = git@github.com:smanoni/timer_unit.git
+	branch = sm/cp-lint
 [submodule "hw/ips/udma_core"]
 	path = hw/ips/udma_core
 	url = https://github.com/pulp-platform/udma_core.git

diff --git a/Bender.yml b/Bender.yml
@@ -36,7 +36,7 @@ dependencies:
   wdt: { path: "hw/ips/wdt" }
   axi2mem: { path: "hw/ips/axi2mem" }
   common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.29.0 }
-  jtag_pulp: { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.3.0 }
+  jtag_pulp: { git: "git@github.com:smanoni/jtag_pulp.git", rev: "sm/lint" }
   idma: { git: "https://github.com/pulp-platform/idma.git", rev: 5af5d10 }
   pulp_soc: { git: "https://github.com/pulp-platform/pulp_soc.git", rev: "control-pulp" }
   pulp_cluster: { git: "https://github.com/pulp-platform/pulp_cluster.git", rev: "control-pulp" }

diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -5,6 +5,21 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 ## Unreleased
 
+## [5.4.0] - 2026-02-12
+### DARE v2.2 Release
+### Added
+- Lint flow based on Slang and Spyglass
+
+### Changed
+- Updated tc_sram dependency (memory macros sim-only models) to avoid
+  unsythesizable errors in Spyglass. pragma translate on/off has been 
+  added to the whole module resulting in 'empty module' error, to be waived
+  in linting, to be properly addressed during backend.
+- Updated SIM_STDOUT default param of pms_top to 0, to avoid instantiation of tbs
+  in Spyglass where is not possible to drive top-level parameters externally.
+- Exposed testmode_i of axi_to_reg instance in axi_scmi_mailbox module. Tied 
+  it to zero in control_pulp_fpga, as currently DFT is disabled in our FPGA platform.
+
 ## [5.3.0] - 2022-04-07
 ### Added
 - Add switch between cluster and non-cluster configuration: elaboration time

diff --git a/hw/includes/cluster_bus_defines.sv b/hw/includes/cluster_bus_defines.sv
@@ -19,10 +19,10 @@
 
 // CLUSTER BUS PARAMETRES
 
-`define NB_SLAVE  4
-`define NB_MASTER 3
+`define CLUSTER_BUS_NB_SLAVE  4
+`define CLUSTER_BUS_NB_MASTER 3
 
-`define NB_REGION 1
+`define CLUSTER_BUS_NB_REGION 1
 
 // MSTER PORT TO TCDM
 `define MASTER_0_START_ADDR 32'h1000_0000

diff --git a/hw/includes/instr_bus_defines.sv b/hw/includes/instr_bus_defines.sv
@@ -20,7 +20,7 @@
 // INSTRUCTION BUS PARAMETRES
 
 // L2
-`define NB_REGION 2
+`define INSTR_BUS_NB_REGION 2
 
 `define MASTER_0_REGION_0_START_ADDR 32'h1A00_0000
 `define MASTER_0_REGION_0_END_ADDR   32'h1DFF_FFFF

diff --git a/hw/includes/soc_bus_defines.sv b/hw/includes/soc_bus_defines.sv
@@ -17,9 +17,9 @@
 // SOC BUS PARAMETRES
 `include "pulp_soc_defines.sv"
 
-`define NB_SLAVE  4
-`define NB_MASTER 4
-`define NB_REGION 4
+`define SOC_BUS_NB_SLAVE  4
+`define SOC_BUS_NB_MASTER 4
+`define SOC_BUS_NB_REGION 4
 
 // MASTER PORT TO CLUSTER(3MB)
 `define CLUSTER_DATA_START_ADDR  32'h1000_0000

diff --git a/hw/ips/axi b/hw/ips/axi
diff --git a/hw/ips/cluster_peripherals b/hw/ips/cluster_peripherals
diff --git a/hw/ips/common_cells b/hw/ips/common_cells
diff --git a/hw/ips/cv32e40p b/hw/ips/cv32e40p
diff --git a/hw/ips/event_unit_flex b/hw/ips/event_unit_flex
diff --git a/hw/ips/idma b/hw/ips/idma
diff --git a/hw/ips/jtag_pulp b/hw/ips/jtag_pulp
diff --git a/hw/ips/pulp_cluster b/hw/ips/pulp_cluster
diff --git a/hw/ips/timer_unit b/hw/ips/timer_unit
diff --git a/hw/ips/udma_i2c b/hw/ips/udma_i2c
diff --git a/hw/ips/udma_qspi b/hw/ips/udma_qspi
diff --git a/hw/ips/udma_uart b/hw/ips/udma_uart
diff --git a/hw/pulp/control_pulp.sv b/hw/pulp/control_pulp.sv
@@ -203,7 +203,7 @@ module control_pulp import control_pulp_pkg::*; #(
   localparam int unsigned AXI_CLUSTER_SOC_DATA_WIDTH = 64;
   localparam int unsigned AXI_SOC_CLUSTER_DATA_WIDTH = 32;
   localparam int unsigned AXI_SOC_CLUSTER_ID_WIDTH   = pkg_soc_interconnect::AXI_ID_OUT_WIDTH; // = 1 + clog2(13) = 5
-  localparam int unsigned AXI_CLUSTER_SOC_ID_WIDTH   = AXI_SOC_CLUSTER_ID_WIDTH + $clog2(`NB_SLAVE); // = 5 + clog2(4) = 7;
+  localparam int unsigned AXI_CLUSTER_SOC_ID_WIDTH   = AXI_SOC_CLUSTER_ID_WIDTH + $clog2(`SOC_BUS_NB_SLAVE); // = 5 + clog2(4) = 7;
 
   localparam int unsigned AXI_USER_WIDTH             = 6;
   localparam int unsigned AXI_CLUSTER_SOC_STRB_WIDTH = AXI_CLUSTER_SOC_DATA_WIDTH/8;

diff --git a/hw/pulp/system_clk_rst_gen.sv b/hw/pulp/system_clk_rst_gen.sv
@@ -89,16 +89,19 @@ module system_clk_rst_gen (
 
   // ref_clk -> divider -> 32 Khz timer clock
   // fixed division by integer factor
-  clk_div #(
-    .RATIO(3125)  // TODO: ADJUST RATIO to match ref clk
-                  // 100 Mhz / 32 Khz = 3125
-  ) i_clk_div_timer (
-    .clk_i     (ref_clk_i),
-    .rst_ni    (rstn_glob_i),
-    .testmode_i(test_mode_i),
-    .en_i      (1'b1),           // TODO: maybe we can map this to reg
-    .clk_o     (clk_for_slow)
-  );
+  clk_int_div #(
+    .DIV_VALUE_WIDTH($clog2(3125+1)),
+    .DEFAULT_DIV_VALUE(3125)
+  ) i_clk_div_timer(
+    .clk_i           ( ref_clk_i    ),
+    .rst_ni          ( rstn_glob_i  ),
+    .test_mode_en_i  ( test_mode_i  ),
+    .en_i            ( 1'b1         ), // TODO: maybe we can map this to reg 
+    .div_i           (  '1          ),
+    .div_valid_i     ( 1'b0         ),
+    .div_ready_o     (              ),
+    .clk_o           ( clk_for_slow )
+  ); 
 
   // Allow clock muxing if dividers are faulty: ref_clk passthrough
   pulp_clock_mux2 i_clk_mux_soc (
+25 −29		icache_ctrl_unit/icache_ctrl_unit.sv
+21 −26		icache_ctrl_unit/mp_icache_ctrl_unit.sv
+36 −42		icache_ctrl_unit/mp_pf_icache_ctrl_unit.sv
+20 −23		icache_ctrl_unit/new_icache_ctrl_unit.sv
+21 −22		icache_ctrl_unit/pri_icache_ctrl_unit.sv
+44 −49		icache_ctrl_unit/sp_icache_ctrl_unit.sv
+1 −1		src/systems/pulpopen/dmac_wrap_cl_idma.sv
+1 −1		src/systems/pulpopen/dmac_wrap_fc_idma.sv
+2 −2		rtl/cluster_bus_wrap.sv
+1 −0		rtl/cluster_interconnect_wrap.sv
+49 −0		rtl/udma_i2c_control.sv
+33 −0		rtl/udma_i2c_reg_if.sv
+49 −0		rtl/udma_i2c_top.sv