WLAST is ignored when FSM is in WAIT_WVALID

[suehtamacv]

There seems to be an issue in the WAIT_WVALID state:

axi_mem_if/src/axi2mem.sv

Lines 160 to 171 in 4d05b1f

	WAIT_WVALID: begin
	slave.w_ready = 1'b1;
	addr_o = ax_req_q.addr;
	// we can now make our first request
	if (slave.w_valid) begin
	req_o = 1'b1;
	we_o = 1'b1;
	state_d = (slave.w_last) ? SEND_B : WRITE;
	cnt_d = 1;
	state_d = WRITE;
	end
	end

Once in this state, the FSM jumps unconditionally to WRITE, regardless of the value of w_last. Under certain conditions, this prevents the b_valid signal to be sent, which might lead to a deadlock.