final commit

README

@@ -0,0 +1,3 @@
+Implementation: Multi-cycle, full modularization.
+
+Intruction fetch file is included but did not use.

eval.sv

@@ -41,24 +41,34 @@ module evaluator();
         // end
 
        // Monitor outputs
-        while (!halt) begin
-        // for (int i = 0; i < 100; i++) begin
-            // Display output data when out_signal is active
-            if (out_signal) begin
-                $display("OUTPUT DATA: %h", out_data);
-            end
+        // while (!halt) begin
+        // // for (int i = 0; i < 100; i++) begin
+        //     // Display output data when out_signal is active
+        //     if (out_signal) begin
+        //         $display("OUTPUT DATA: %h", out_data);
+        //         $display("HALT: %h", halt);
+        //     end
 
-            // Add more monitoring as needed
+        //     // Add more monitoring as needed
 
-            // Wait for a clock cycle
-            #1;
-        end
-        // #100;
+        //     // Wait for a clock cycle
+        //     #1;
+        // end
+        // // #100;
 
-        // Simulation finished
-        $display("Simulation finished. Halt signal received.");
-        // $display("output %d\n", out_data);
-        // $display("halted %h\n", halt);
+        // // Simulation finished
+        // $display("Simulation finished. Halt signal received.");
+        // $display("OUTPUT DATA: %h", out_data);
+        // $display("OUTPUT SIGNAL: %h", out_signal);
+        // $display("HALT: %h", halt);
+        // // $display("output %d\n", out_data);
+        // // $display("halted %h\n", halt);
+         while(halt != 1) begin
+            if(out_signal == 1) begin
+                $display("Output: %d", out_data);
+            end
+            #10;
+        end 
 
 
         $finish;

mod/alu.sv

@@ -1,5 +1,6 @@
-//8-bit arithmetic and logical unit
+// 64-bit ALU
 module alu(
+	input logic [3:0] state, // State of the CPU
     input logic [63:0] operand1, // operand 1
     input logic [63:0] operand2, // operand 2
     input logic [4:0] op,  // Operation code and control signal
@@ -14,10 +15,10 @@ real a_real;
 real b_real;
 
 always @(*) begin
-	a = operand1;
-	b = operand2;
-	a_real = a;
-	b_real = b;
+	a <= operand1;
+	b <= operand2;
+	a_real <= $bitstoreal(a);
+	b_real <= $bitstoreal(b);
 
 	if (pass) begin
 		result = (a == 1'bz)? b : a; // Pass signal 
@@ -26,52 +27,57 @@ always @(*) begin
 		// Perform operation based on operation code
 		case (op)
 			// Integer Arithmetic Instructions
-			6'b000000: // add rd, rs, rt
+			5'h0: // add rd, rs, rt
 				result = a + b;
-			6'b000001: // addi rd, L
+			5'h1: // addi rd, L
 				result = a + b;
-			6'b000010: // sub rd, rs, rt
+			5'h2: // sub rd, rs, rt
 				result = a - b;
-			6'b000011: // subi rd, L
+			5'h3: // subi rd, L
 				result = a - b;
-			6'b000100: // mul rd, rs, rt
+			5'h4: // mul rd, rs, rt
 				result = a * b;
-			6'b000101: // div rd, rs, rt
-				if (b == 0)
+			5'h5: // div rd, rs, rt
+				if (b == 0 && state == 3'b010) // Check if the state is in the CPU state
 					error = 1;
 				else
 					result = a / b;
 
 			// Logic Instructions
-			6'b000110: // and rd, rs, rt
+			5'h6: // and rd, rs, rt
 				result = a & b;
-			6'b000111: // or rd, rs, rt
+			5'h7: // or rd, rs, rt
 				result = a | b;
-			6'b001000: // xor rd, rs, rt
+			5'h8: // xor rd, rs, rt
 				result = a ^ b;
-			6'b001001: // not rd, rs
+			5'h9: // not rd, rs
 				result = ~a;
-			6'b001010: // shftr rd, rs, rt
+			5'ha: // shftr rd, rs, rt
 				result = a >> b;
-			6'b001011: // shftl rd, rs, rt
-				result = a << b;
-			6'b001100: // shftri rd, L
+			5'hb: // shftri rd, L
 				result = a >> b;
-			6'b001101: // shftli rd, L
+			5'hc: // shftl rd, rs, rt
+				result = a << b;
+			5'hd: // shftli rd, L
 				result = a << b;
 
 			// Floating Point Instructions
-			6'h19: // fadd rd, rs, rt
-				result = a_real + b_real;
-			6'h1a: // fsub rd, rs, rt
-				result = a_real - b_real;
-			6'h1b: // fmul rd, rs, rt
-				result = a_real * b_real;
-			6'h1c: // fdiv rd, rs, rt
-				if (b_real == 0)
+			5'h19: // fadd rd, rs, rt
+				result = $realtobits(a_real + b_real);
+			5'h1a: // fsub rd, rs, rt
+				result = $realtobits(a_real - b_real);
+			5'h1b: // fmul rd, rs, rt
+				result = $realtobits(a_real * b_real);
+			5'h1c: // fdiv rd, rs, rt
+				if (b_real == 0 && state == 3'b010)
 					error = 1;
 				else
-					result = a_real / b_real;
+					result = $realtobits(a_real / b_real);
+
+			5'h17: begin // MOVRL
+				result = a;
+				result[11:0] = b[11:0];
+			end
 		endcase
 	end
 end