phoenix-rtos · adamgreloch · May 30, 2025 · Jul 3, 2025 · May 16, 2025 · Sep 11, 2025
diff --git a/Makefile b/Makefile
@@ -58,6 +58,7 @@ include posix/Makefile
 include lib/Makefile
 include test/Makefile
 include log/Makefile
+include perf/Makefile
 
 # incremental build quick-fix, WARN: assuming the sources are in c
 DEPS := $(patsubst %.o, %.c.d, $(OBJS))

diff --git a/hal/aarch64/interrupts_gicv2.c b/hal/aarch64/interrupts_gicv2.c
@@ -25,6 +25,9 @@
 #include "dtb.h"
 #include "interrupts_gicv2.h"
 #include "arch/pmap.h"
+#include "config.h"
+
+#include "perf/trace-events.h"
 
 #define SPI_FIRST_IRQID 32
 
@@ -87,6 +90,7 @@ struct {
 	spinlock_t spinlock[SIZE_INTERRUPTS];
 	intr_handler_t *handlers[SIZE_INTERRUPTS];
 	unsigned int counters[SIZE_INTERRUPTS];
+	int trace_irqs;
 } interrupts_common;
 
 
@@ -100,6 +104,7 @@ int interrupts_dispatch(unsigned int n, cpu_context_t *ctx)
 	intr_handler_t *h;
 	int reschedule = 0;
 	spinlock_ctx_t sc;
+	int trace;
 
 	u32 ciarValue = *(interrupts_common.gicc + gicc_iar);
 	n = ciarValue & 0x3ff;
@@ -108,6 +113,11 @@ int interrupts_dispatch(unsigned int n, cpu_context_t *ctx)
 		return 0;
 	}
 
+	trace = interrupts_common.trace_irqs != 0 && n != TIMER_IRQ_ID;
+	if (trace != 0) {
+		trace_eventInterruptEnter(n);
+	}
+
 	hal_spinlockSet(&interrupts_common.spinlock[n], &sc);
 
 	interrupts_common.counters[n]++;
@@ -126,6 +136,10 @@ int interrupts_dispatch(unsigned int n, cpu_context_t *ctx)
 
 	hal_spinlockClear(&interrupts_common.spinlock[n], &sc);
 
+	if (trace != 0) {
+		trace_eventInterruptExit(n);
+	}
+
 	return reschedule;
 }
 
@@ -238,12 +252,20 @@ int hal_interruptsDeleteHandler(intr_handler_t *h)
 }
 
 
+void _hal_interruptsTrace(int enable)
+{
+	interrupts_common.trace_irqs = !!enable;
+}
+
+
 /* Function initializes interrupt handling */
 void _hal_interruptsInit(void)
 {
 	u32 i;
 	addr_t gicc, gicd;
 
+	interrupts_common.trace_irqs = 0;
+
 	dtb_getGIC(&gicc, &gicd);
 	interrupts_common.gicd = _pmap_halMapDevice(gicd, 0, SIZE_PAGE);
 	interrupts_common.gicc = _pmap_halMapDevice(gicc, 0, SIZE_PAGE);

diff --git a/hal/aarch64/zynqmp/config.h b/hal/aarch64/zynqmp/config.h
@@ -24,6 +24,7 @@
 #define ASID_BITS       16
 #define NUM_CPUS        4
 #define SIZE_INTERRUPTS 188
+#define TIMER_IRQ_ID    68
 
 #ifndef __ASSEMBLY__
 

diff --git a/hal/aarch64/zynqmp/timer.c b/hal/aarch64/zynqmp/timer.c
@@ -21,11 +21,11 @@
 
 #include "hal/aarch64/arch/pmap.h"
 #include "zynqmp.h"
+#include "config.h"
 
 
 #define TTC0_BASE_ADDR       ((addr_t)0x00ff110000)
 #define TIMER_SRC_CLK_CPU_1x 99990000
-#define TIMER_IRQ_ID         68
 
 struct {
 	volatile u32 *ttc;

diff --git a/hal/arm/rtt.c b/hal/arm/rtt.c
@@ -26,6 +26,14 @@
 #define RTT_CB_SIZE 256
 #endif
 
+#ifndef RTT_ENABLED
+#define RTT_ENABLED 0
+#endif
+
+#ifndef RTT_ENABLED_PLO
+#define RTT_ENABLED_PLO 0
+#endif
+
 
 struct rtt_pipe {
 	const char *name;
@@ -140,10 +148,33 @@ int _hal_rttReset(unsigned int chan, rtt_dir_t dir)
 }
 
 
+int _hal_rttIsReady(void)
+{
+	return common.rtt != NULL;
+}
+
+
 int _hal_rttInit(void)
 {
-	const syspage_map_t *map = syspage_mapNameResolve(RTT_SYSPAGE_MAP_NAME);
+	common.rtt = NULL;
+	return 0;
+}
+
+
+int _hal_rttSetup(void)
+{
+	const syspage_map_t *map;
 
+	if (_hal_rttIsReady() != 0) {
+		/* RTT already set up */
+		return 0;
+	}
+
+	if (RTT_ENABLED == 0 || RTT_ENABLED_PLO == 0) {
+		return -ENOSYS;
+	}
+
+	map = syspage_mapNameResolve(RTT_SYSPAGE_MAP_NAME);
 	if (map == NULL) {
 		return -ENOENT;
 	}
@@ -154,5 +185,6 @@ int _hal_rttInit(void)
 
 	/* TODO: Place CB always at the start of the map? */
 	common.rtt = (void *)(map->end - RTT_CB_SIZE);
+
 	return 0;
 }
diff --git a/hal/arm/rtt.h b/hal/arm/rtt.h
@@ -32,6 +32,10 @@ typedef enum {
 int _hal_rttInit(void);
 
 
+/* Setup rtt based on syspage map */
+int _hal_rttSetup(void);
+
+
 /* Non-blocking write to channel */
 int _hal_rttWrite(unsigned int chan, const void *buf, unsigned int count);
 

diff --git a/hal/armv7a/imx6ull/config.h b/hal/armv7a/imx6ull/config.h
@@ -21,6 +21,8 @@
 
 #define NUM_CPUS 1
 
+#define TIMER_IRQ_ID 88
+
 #ifndef __ASSEMBLY__
 
 #define HAL_NAME_PLATFORM "NXP i.MX 6ULL "

diff --git a/hal/armv7a/imx6ull/interrupts.c b/hal/armv7a/imx6ull/interrupts.c
@@ -16,9 +16,12 @@
 #include "hal/cpu.h"
 #include "hal/interrupts.h"
 #include "hal/list.h"
+#include "config.h"
 
 #include "proc/userintr.h"
 
+#include "perf/trace-events.h"
+
 #define SIZE_INTERRUPTS 159
 
 enum { /* 1024 reserved */ ctlr = 0x400, typer, iidr, /* 29 reserved */ igroupr0 = 0x420, /* 16 registers */
@@ -38,6 +41,7 @@ struct {
 	spinlock_t spinlock[SIZE_INTERRUPTS];
 	intr_handler_t *handlers[SIZE_INTERRUPTS];
 	unsigned int counters[SIZE_INTERRUPTS];
+	int trace_irqs;
 } interrupts;
 
 
@@ -51,6 +55,7 @@ int interrupts_dispatch(unsigned int n, cpu_context_t *ctx)
 	intr_handler_t *h;
 	int reschedule = 0;
 	spinlock_ctx_t sc;
+	int trace;
 
 	u32 iarValue = *(interrupts.gic + iar);
 	n = iarValue & 0x3ff;
@@ -59,6 +64,11 @@ int interrupts_dispatch(unsigned int n, cpu_context_t *ctx)
 		return 0;
 	}
 
+	trace = interrupts.trace_irqs != 0 && n != TIMER_IRQ_ID;
+	if (trace != 0) {
+		trace_eventInterruptEnter(n);
+	}
+
 	hal_spinlockSet(&interrupts.spinlock[n], &sc);
 
 	interrupts.counters[n]++;
@@ -76,6 +86,10 @@ int interrupts_dispatch(unsigned int n, cpu_context_t *ctx)
 
 	hal_spinlockClear(&interrupts.spinlock[n], &sc);
 
+	if (trace != 0) {
+		trace_eventInterruptExit(n);
+	}
+
 	return reschedule;
 }
 
@@ -163,10 +177,18 @@ int hal_interruptsDeleteHandler(intr_handler_t *h)
 }
 
 
+void _hal_interruptsTrace(int enable)
+{
+	interrupts.trace_irqs = !!enable;
+}
+
+
 void _hal_interruptsInit(void)
 {
 	u32 i, t, priority;
 
+	interrupts.trace_irqs = 0;
+
 	for (i = 0; i < SIZE_INTERRUPTS; ++i) {
 		interrupts.handlers[i] = NULL;
 		interrupts.counters[i] = 0;

diff --git a/hal/armv7a/imx6ull/timer.c b/hal/armv7a/imx6ull/timer.c
@@ -17,8 +17,7 @@
 #include "hal/timer.h"
 #include "hal/spinlock.h"
 #include "hal/string.h"
-
-#define TIMER_IRQ_ID 88
+#include "config.h"
 
 struct {
 	volatile u32 *epit1;

diff --git a/hal/armv7a/zynq7000/config.h b/hal/armv7a/zynq7000/config.h
@@ -29,6 +29,8 @@
 
 #define NUM_CPUS 2
 
+#define TIMER_IRQ_ID 42
+
 #ifndef __ASSEMBLY__
 
 #define HAL_NAME_PLATFORM "Xilinx Zynq-7000 "

diff --git a/hal/armv7a/zynq7000/interrupts.c b/hal/armv7a/zynq7000/interrupts.c
@@ -19,9 +19,11 @@
 #include "hal/spinlock.h"
 #include "hal/interrupts.h"
 #include "hal/list.h"
+#include "config.h"
 
 #include "proc/userintr.h"
 
+#include "perf/trace-events.h"
 
 #define SIZE_INTERRUPTS 95
 #define SPI_FIRST_IRQID 32
@@ -57,6 +59,7 @@ struct {
 	spinlock_t spinlock[SIZE_INTERRUPTS];
 	intr_handler_t *handlers[SIZE_INTERRUPTS];
 	unsigned int counters[SIZE_INTERRUPTS];
+	int trace_irqs;
 } interrupts_common;
 
 
@@ -84,6 +87,7 @@ int interrupts_dispatch(unsigned int n, cpu_context_t *ctx)
 	intr_handler_t *h;
 	int reschedule = 0;
 	spinlock_ctx_t sc;
+	int trace;
 
 	u32 ciarValue = *(interrupts_common.gic + ciar);
 	n = ciarValue & 0x3ff;
@@ -92,6 +96,11 @@ int interrupts_dispatch(unsigned int n, cpu_context_t *ctx)
 		return 0;
 	}
 
+	trace = interrupts_common.trace_irqs != 0 && n != TIMER_IRQ_ID;
+	if (trace != 0) {
+		trace_eventInterruptEnter(n);
+	}
+
 	hal_spinlockSet(&interrupts_common.spinlock[n], &sc);
 
 	interrupts_common.counters[n]++;
@@ -109,6 +118,10 @@ int interrupts_dispatch(unsigned int n, cpu_context_t *ctx)
 
 	hal_spinlockClear(&interrupts_common.spinlock[n], &sc);
 
+	if (trace != 0) {
+		trace_eventInterruptExit(n);
+	}
+
 	return reschedule;
 }
 
@@ -205,11 +218,19 @@ int hal_interruptsDeleteHandler(intr_handler_t *h)
 }
 
 
+void _hal_interruptsTrace(int enable)
+{
+	interrupts_common.trace_irqs = !!enable;
+}
+
+
 /* Function initializes interrupt handling */
 void _hal_interruptsInit(void)
 {
 	u32 i;
 
+	interrupts_common.trace_irqs = 0;
+
 	for (i = 0; i < SIZE_INTERRUPTS; ++i) {
 		interrupts_common.handlers[i] = NULL;
 		interrupts_common.counters[i] = 0;

diff --git a/hal/armv7a/zynq7000/timer.c b/hal/armv7a/zynq7000/timer.c
@@ -17,11 +17,11 @@
 #include "hal/timer.h"
 #include "hal/spinlock.h"
 #include "hal/string.h"
+#include "config.h"
 
 #include "zynq.h"
 
 #define TIMER_SRC_CLK_CPU_1x 111111115 /* Hz */
-#define TIMER_IRQ_ID         42
 
 struct {
 	volatile u32 *ttc;

diff --git a/hal/armv7m/imxrt/10xx/console.c b/hal/armv7m/imxrt/10xx/console.c
@@ -186,7 +186,7 @@ static void _hal_uartInit(void)
 void _hal_consoleInit(void)
 {
 #if RTT_ENABLED && !ISEMPTY(RTT_CONSOLE_KERNEL)
-	_hal_rttInit();
+	_hal_rttSetup();
 #endif
 
 #if !ISEMPTY(UART_CONSOLE_KERNEL)

diff --git a/hal/armv7m/imxrt/10xx/imxrt10xx.c b/hal/armv7m/imxrt/10xx/imxrt10xx.c
@@ -21,6 +21,7 @@
 #include "include/arch/armv7m/imxrt/10xx/imxrt10xx.h"
 
 #include "hal/arm/scs.h"
+#include "hal/arm/rtt.h"
 
 #include "imxrt10xx.h"
 #include "config.h"
@@ -1926,6 +1927,7 @@ void _imxrt_init(void)
 	imxrt_common.cpuclk = 528000000; /* Default system clock */
 
 	_hal_scsInit();
+	_hal_rttInit();
 
 	/* Disable watchdogs */
 	if ((*(imxrt_common.wdog1 + wdog_wcr) & (1 << 2)) != 0) {

diff --git a/hal/armv7m/imxrt/117x/console.c b/hal/armv7m/imxrt/117x/console.c
@@ -187,7 +187,7 @@ static void _hal_uartInit(void)
 void _hal_consoleInit(void)
 {
 #if RTT_ENABLED && !ISEMPTY(RTT_CONSOLE_KERNEL)
-	_hal_rttInit();
+	_hal_rttSetup();
 #endif
 
 #if !ISEMPTY(UART_CONSOLE_KERNEL)

diff --git a/hal/armv7m/imxrt/117x/imxrt117x.c b/hal/armv7m/imxrt/117x/imxrt117x.c
@@ -24,6 +24,7 @@
 
 #include "hal/arm/barriers.h"
 #include "hal/arm/scs.h"
+#include "hal/arm/rtt.h"
 
 #include <board_config.h>
 
@@ -776,6 +777,7 @@ void _imxrt_init(void)
 	imxrt_common.cpuclk = 696000000;
 
 	_hal_scsInit();
+	_hal_rttInit();
 
 	/* WDOG1 and WDOG2 can't be disabled once enabled */