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Identify hypervisor (#107)
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Identify the hypervisor, if any, using CPUID leaf 0x40000000.
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phaubertin authored Jan 12, 2025
1 parent 1cd5b71 commit 9b2f389
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1 change: 1 addition & 0 deletions .github/workflows/build-i686.yml
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Expand Up @@ -14,6 +14,7 @@ jobs:
cc: [gcc, clang]

runs-on: ubuntu-latest
timeout-minutes: 5

env:
MAKE: make CC="${{ matrix.cc }} -Werror"
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2 changes: 1 addition & 1 deletion COPYING
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@@ -1,4 +1,4 @@
Copyright (C) 2019-2024 Philippe Aubertin.
Copyright (C) 2019-2025 Philippe Aubertin.
All rights reserved.

Redistribution and use in source and binary forms, with or without
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72 changes: 54 additions & 18 deletions include/kernel/infrastructure/i686/asm/cpuid.h
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/*
* Copyright (C) 2019-2024 Philippe Aubertin.
* Copyright (C) 2019-2025 Philippe Aubertin.
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
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#ifndef JINUE_KERNEL_INFRASTRUCTURE_I686_ASM_CPUID_H
#define JINUE_KERNEL_INFRASTRUCTURE_I686_ASM_CPUID_H

/* Basic leaf 0 (0x00000001) ebx, ecx, edx */
/* Basic leaf 0 (0x00000000)
*
* Note be careful about the register order: the signature is in ebx, edx, ecx
* in this order. */

#define CPUID_VENDOR_AMD_DW0 0x68747541 /* Auth */
#define CPUID_VENDOR_AMD_DW1 0x69746e65 /* enti */
#define CPUID_VENDOR_AMD_DW2 0x444d4163 /* cAMD */
#define CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
#define CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
#define CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */

#define CPUID_VENDOR_INTEL_DW0 0x756e6547 /* Genu */
#define CPUID_VENDOR_INTEL_DW1 0x49656e69 /* ineI */
#define CPUID_VENDOR_INTEL_DW2 0x6c65746e /* ntel */
#define CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
#define CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
#define CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */

/* Basic leaf 1 (0x00000001) ecx */

#define CPUID_FEATURE_HYPERVISOR (1<<31)

/* Basic leaf 1 (0x00000001) edx */

#define CPUID_FEATURE_FPU (1<<0)
#define CPUID_FEATURE_FPU (1<<0)

#define CPUID_FEATURE_PSE (1<<3)

#define CPUID_FEATURE_PAE (1<<6)

#define CPUID_FEATURE_APIC (1<<9)

#define CPUID_FEATURE_SEP (1<<11)

#define CPUID_FEATURE_PGE (1<<13)

#define CPUID_FEATURE_CLFLUSH (1<<19)

#define CPUID_FEATURE_HTT (1<<28)

/* Software/hypervisor leaf 0 (0x40000000) ebx, ecx, edx */


#define CPUID_FEATURE_PSE (1<<3)
#define CPUID_HYPERVISOR_ACRN 0x4e524341 /* ACRN */

#define CPUID_FEATURE_PAE (1<<6)
#define CPUID_HYPERVISOR_BHYVE_EBX 0x76796862 /* bhyv */
#define CPUID_HYPERVISOR_BHYVE_ECX 0x68622065 /* e bh */
#define CPUID_HYPERVISOR_BHYVE_EDX 0x20657679 /* hyve */

#define CPUID_FEATURE_APIC (1<<9)
#define CPUID_HYPERVISOR_KVM_EBX 0x4b4d564b /* KVMK */
#define CPUID_HYPERVISOR_KVM_ECX 0x564b4d56 /* VMKV */
#define CPUID_HYPERVISOR_KVM_EDX 0x0000004d /* M */

#define CPUID_FEATURE_SEP (1<<11)
#define CPUID_HYPERVISOR_HYPER_V_EBX 0x7263694d /* Micr */
#define CPUID_HYPERVISOR_HYPER_V_ECX 0x666f736f /* osof */
#define CPUID_HYPERVISOR_HYPER_V_EDX 0x76482074 /* t Hv */

#define CPUID_FEATURE_PGE (1<<13)
#define CPUID_HYPERVISOR_QEMU_EBX 0x54474354 /* TCGT */
#define CPUID_HYPERVISOR_QEMU_ECX 0x43544743 /* CGTC */
#define CPUID_HYPERVISOR_QEMU_EDX 0x47435447 /* GTCG */

#define CPUID_FEATURE_CLFLUSH (1<<19)
#define CPUID_HYPERVISOR_VMWARE_EBX 0x61774d56 /* VMwa */
#define CPUID_HYPERVISOR_VMWARE_ECX 0x4d566572 /* reVM */
#define CPUID_HYPERVISOR_VMWARE_EDX 0x65726177 /* ware */

#define CPUID_FEATURE_HTT (1<<28)
#define CPUID_HYPERVISOR_XEN_EBX 0x566e6558 /* XenV */
#define CPUID_HYPERVISOR_XEN_ECX 0x65584d4d /* MMXe */
#define CPUID_HYPERVISOR_XEN_EDX 0x4d4d566e /* nVMM */

/* Extended leaf 1 (0x8000001) edx */

#define CPUID_EXT_FEATURE_SYSCALL (1<<11)
#define CPUID_EXT_FEATURE_SYSCALL (1<<11)

#define CPUID_FEATURE_NXE (1<<20)
#define CPUID_FEATURE_NXE (1<<20)

#endif
22 changes: 21 additions & 1 deletion include/kernel/infrastructure/i686/asm/cpuinfo.h
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/*
* Copyright (C) 2019-2024 Philippe Aubertin.
* Copyright (C) 2019-2025 Philippe Aubertin.
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
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#define CPUINFO_VENDOR_INTEL 2

/* hypervisors */

#define HYPERVISOR_ID_NONE 0

#define HYPERVISOR_ID_UNKNOWN 1

#define HYPERVISOR_ID_ACRN 2

#define HYPERVISOR_ID_BHYVE 3

#define HYPERVISOR_ID_HYPER_V 4

#define HYPERVISOR_ID_KVM 5

#define HYPERVISOR_ID_QEMU 6

#define HYPERVISOR_ID_VMWARE 7

#define HYPERVISOR_ID_XEN 8

#endif
3 changes: 2 additions & 1 deletion include/kernel/infrastructure/i686/cpuinfo.h
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2019-2024 Philippe Aubertin.
* Copyright (C) 2019-2025 Philippe Aubertin.
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
Expand Down Expand Up @@ -41,6 +41,7 @@ typedef struct {
unsigned int dcache_alignment;
uint32_t features;
int vendor;
int hypervisor;
unsigned int family;
unsigned int model;
unsigned int stepping;
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13 changes: 0 additions & 13 deletions include/kernel/infrastructure/i686/isa/instrs.h
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Expand Up @@ -41,19 +41,6 @@ typedef struct {
uint32_t edx;
} x86_cpuid_regs_t;

typedef struct {
x86_cpuid_regs_t basic0;
x86_cpuid_regs_t basic1;
x86_cpuid_regs_t ext0;
x86_cpuid_regs_t ext1;
x86_cpuid_regs_t ext2;
x86_cpuid_regs_t ext3;
x86_cpuid_regs_t ext4;
x86_cpuid_regs_t ext8;
bool ext4_valid;
bool ext8_valid;
} x86_cpuid_leafs;

void cli(void);

void sti(void);
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