Refactor to remove submodule instantiation parsing

multiply_add.sus

@@ -194,10 +194,10 @@ module multiply_add :
 
 
 module pow17 : int i -> int o {
-	    int i2  = i * i
-	reg int i4  = i2 * i2
-	    int i8  = i4 * i4
-	reg int i16 = i8 * i8
+	    int i2  = i   * i
+	reg int i4  = i2  * i2
+	    int i8  = i4  * i4
+	reg int i16 = i8  * i8
 	        o   = i16 * i
 }
 
@@ -242,18 +242,14 @@ module Tree_Multiply : int[4] values -> int total {
 	reg total = a * b
 }
 
-
-
-
-//timeline (X, false -> /)* .. (X, true -> T)
 module Accumulator : int term, bool done -> int total {
     state int tot
 	initial tot = 0
 
     int new_tot = tot + term
     if done {
         reg total = new_tot
-        tot = 0 // Must restore initial conditions
+        tot = 0
     } else {
         tot = new_tot
     }
@@ -479,7 +475,7 @@ module bad_cycle : int a -> int r {
 
 	r = new_test
 }
-module test {}
+
 module module_taking_time : 
 	int i'0 -> int o'5 {
 	o = i

philosophy/images/fifoWritePort.drawio

@@ -0,0 +1,26 @@
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+  <diagram name="Page-1" id="l-DM_fYlzvVIUVRDgFh1">
+    <mxGraphModel dx="190" dy="259" grid="1" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="827" pageHeight="1169" math="0" shadow="0">
+      <root>
+        <mxCell id="0" />
+        <mxCell id="1" parent="0" />
+        <mxCell id="jyQOK9qtBp4xA-2xft1N-2" value="" style="endArrow=none;html=1;rounded=0;" edge="1" parent="1">
+          <mxGeometry width="50" height="50" relative="1" as="geometry">
+            <mxPoint x="440" y="560" as="sourcePoint" />
+            <mxPoint x="440" y="400" as="targetPoint" />
+            <Array as="points">
+              <mxPoint x="360" y="560" />
+              <mxPoint x="360" y="400" />
+            </Array>
+          </mxGeometry>
+        </mxCell>
+        <mxCell id="jyQOK9qtBp4xA-2xft1N-3" value="" style="ellipse;shape=cloud;whiteSpace=wrap;html=1;fillColor=#f5f5f5;fontColor=#333333;strokeColor=#666666;" vertex="1" parent="1">
+          <mxGeometry x="190" y="400" width="120" height="80" as="geometry" />
+        </mxCell>
+        <mxCell id="jyQOK9qtBp4xA-2xft1N-4" value="" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#fff2cc;strokeColor=#d6b656;" vertex="1" parent="1">
+          <mxGeometry x="220" y="430" width="20" height="30" as="geometry" />
+        </mxCell>
+      </root>
+    </mxGraphModel>
+  </diagram>
+</mxfile>

src/codegen_fallback.rs

@@ -1,4 +1,4 @@
-use std::{iter::zip, ops::Deref};
+use std::ops::Deref;
 
 use crate::{flattening::{Instruction, Module}, instantiation::{ConnectToPathElem, InstantiatedModule, RealWire, RealWireDataSource, WireID}, linker::{get_builtin_type, TypeUUID}, typing::ConcreteType};
 
@@ -95,16 +95,16 @@ impl<'g, 'out, Stream : std::fmt::Write> CodeGenerationContext<'g, 'out, Stream>
         // First output the interface of the module
         writeln!(self.program_text, "module {}(", self.md.link_info.name)?;
         writeln!(self.program_text, "\tinput clk,")?;
-        for (real_port, is_input) in self.instance.interface.iter() {
-            let port_wire = &self.instance.wires[real_port];
-            let input_or_output = if is_input {"input"} else {"output /*mux_wire*/ reg"};
+        for (_id, port) in self.instance.interface_ports.iter() {
+            let port_wire = &self.instance.wires[port.wire];
+            let input_or_output = if port.is_input {"input"} else {"output /*mux_wire*/ reg"};
             let wire_typ = typ_to_verilog_array(&port_wire.typ);
             let wire_name = wire_name_self_latency(port_wire, self.use_latency);
             writeln!(self.program_text, "\t{input_or_output}{wire_typ} {wire_name},")?;
         }
         writeln!(self.program_text, ");\n")?;
-        for (real_port, _is_input) in self.instance.interface.iter() {
-            let port_wire = &self.instance.wires[real_port];
+        for (_id, port) in self.instance.interface_ports.iter() {
+            let port_wire = &self.instance.wires[port.wire];
             self.add_latency_registers(port_wire)?;
         }
 
@@ -166,9 +166,10 @@ impl<'g, 'out, Stream : std::fmt::Write> CodeGenerationContext<'g, 'out, Stream>
             let sm_name = &sm.name;
             writeln!(self.program_text, "{sm_instance_name} {sm_name}(")?;
             writeln!(self.program_text, "\t.clk(clk),")?;
-            for (port, wire) in zip(sm.instance.interface.iter(), sm.wires.iter()) {
-                let port_name = wire_name_self_latency(&sm.instance.wires[port.0], self.use_latency);
-                let wire_name = wire_name_self_latency(&self.instance.wires[wire.0], self.use_latency);
+            for (port_id, port) in &sm.port_map {
+                let iport = &sm.instance.interface_ports[port_id];
+                let port_name = wire_name_self_latency(&sm.instance.wires[iport.wire], self.use_latency);
+                let wire_name = wire_name_self_latency(&self.instance.wires[*port], self.use_latency);
                 writeln!(self.program_text, "\t.{port_name}({wire_name}),")?;
             }
             writeln!(self.program_text, ");")?;

src/compiler_top.rs

@@ -73,5 +73,5 @@ pub fn instantiate(linker : &Linker, module_id : ModuleUUID) -> Option<Rc<Instan
     let md = &linker.modules[module_id];
     println!("Instantiating {}", md.link_info.name);
 
-    md.instantiations.instantiate(&md.link_info.name, &md.flattened, linker)
+    md.instantiations.instantiate(&md.link_info.name, md, linker)
 }

src/dev_aid/lsp.rs

@@ -11,7 +11,7 @@ use crate::{
     compiler_top::{add_file, recompile_all, update_file},
     errors::{CompileError, ErrorCollector, ErrorLevel},
     file_position::{FileText, LineCol, Span},
-    flattening::{FlatID, IdentifierType, Instruction, Module, WireInstance, WireSource},
+    flattening::{ConnectionWriteRoot, FlatID, IdentifierType, Instruction, Module, WireInstance, WireSource},
     instantiation::{SubModuleOrWire, CALCULATE_LATENCY_LATER},
     linker::{FileData, FileUUID, FileUUIDMarker, Linker, NameElem},
     typing::WrittenType,
@@ -57,6 +57,8 @@ impl LoadedFileCache {
 }
 
 pub fn lsp_main(port : u16, debug : bool) -> Result<(), Box<dyn Error + Sync + Send>> {
+    std::env::set_var("RUST_BACKTRACE", "1"); // Enable backtrace because I can't set it in Env vars
+
     println!("starting LSP server");
 
     // Create the transport. Includes the stdio (stdin and stdout) versions but this could
@@ -328,7 +330,16 @@ fn get_info_about_source_location<'linker>(linker : &'linker Linker, position :
                                 location_builder.update(wire.span, loc_info);
                             }
                             Instruction::Write(write) => {
-                                location_builder.update(write.to.root_span, LocationInfo::WireRef(md, write.to.root));
+                                match write.to.root {
+                                    ConnectionWriteRoot::LocalDecl(decl_id) => {
+                                        location_builder.update(write.to.root_span, LocationInfo::WireRef(md, decl_id));
+                                    }
+                                    ConnectionWriteRoot::SubModulePort(port) => {
+                                        if let Some(span) = port.port_name_span {
+                                            todo!("LSP for named ports");
+                                        }
+                                    }
+                                }
                             }
                             Instruction::IfStatement(_) | Instruction::ForStatement(_) => {}
                         };
@@ -461,7 +472,7 @@ fn handle_request(method : &str, params : serde_json::Value, file_cache : &mut L
                 } else {
                     match info {
                         LocationInfo::WireRef(md, decl_id) => {
-                            let decl = md.flattened.instructions[decl_id].extract_wire_declaration();
+                            let decl = md.flattened.instructions[decl_id].unwrap_wire_declaration();
                             let typ_str = decl.typ.to_string(&file_cache.linker.types);
                             let name_str = &decl.name;
 
@@ -503,7 +514,7 @@ fn handle_request(method : &str, params : serde_json::Value, file_cache : &mut L
                 match info {
                     LocationInfo::WireRef(md, decl_id) => {
                         let uri = file_cache.uris[md.link_info.file].clone();
-                        let decl = md.flattened.instructions[decl_id].extract_wire_declaration();
+                        let decl = md.flattened.instructions[decl_id].unwrap_wire_declaration();
                         let range = to_position_range(file_cache.linker.files[md.link_info.file].file_text.get_span_linecol_range(decl.name_span));
                         GotoDefinitionResponse::Scalar(Location{uri, range})
                     }

src/dev_aid/syntax_highlighting.rs

@@ -6,7 +6,7 @@ use crate::{
     compiler_top::{add_file, recompile_all},
     errors::{CompileError, ErrorLevel},
     file_position::Span,
-    flattening::{IdentifierType, Instruction, WireSource},
+    flattening::{ConnectionWriteRoot, IdentifierType, Instruction, WireSource},
     linker::{FileUUID, FileUUIDMarker, Linker, NameElem}
 };
 
@@ -35,8 +35,7 @@ pub fn walk_name_color(all_objects : &[NameElem], linker : &Linker) -> Vec<(IDEI
                         Instruction::Wire(w) => {
                             match &w.source {
                                 &WireSource::WireRead(from_wire) => {
-                                    let decl = module.flattened.instructions[from_wire].extract_wire_declaration();
-                                    if !decl.is_declared_in_this_module {continue;} // Virtual wires don't appear in this program text
+                                    let decl = module.flattened.instructions[from_wire].unwrap_wire_declaration();
                                     result.push((IDEIdentifierType::Value(decl.identifier_type), w.span));
                                 }
                                 WireSource::UnaryOp { op:_, right:_ } => {}
@@ -46,19 +45,31 @@ pub fn walk_name_color(all_objects : &[NameElem], linker : &Linker) -> Vec<(IDEI
                                 WireSource::NamedConstant(_name) => {
                                     result.push((IDEIdentifierType::Constant, w.span));
                                 }
+                                WireSource::PortRead(info) => {
+                                    if let Some(port_name_span) = &info.port_name_span {
+                                        result.push((IDEIdentifierType::Value(info.port_identifier_typ), *port_name_span))
+                                    }
+                                }
                             }
                         }
                         Instruction::Declaration(decl) => {
-                            if !decl.is_declared_in_this_module {continue;} // Virtual wires don't appear in this program text
                             decl.typ_expr.for_each_located_type(&mut |_, span| {
                                 result.push((IDEIdentifierType::Type, span));
                             });
                             result.push((IDEIdentifierType::Value(decl.identifier_type), decl.name_span));
                         }
                         Instruction::Write(conn) => {
-                            let decl = module.flattened.instructions[conn.to.root].extract_wire_declaration();
-                            if !decl.is_declared_in_this_module {continue;} // Virtual wires don't appear in this program text
-                            result.push((IDEIdentifierType::Value(decl.identifier_type), conn.to.root_span));
+                            match conn.to.root {
+                                ConnectionWriteRoot::LocalDecl(decl_id) => {
+                                    let decl = module.flattened.instructions[decl_id].unwrap_wire_declaration();
+                                    result.push((IDEIdentifierType::Value(decl.identifier_type), conn.to.root_span));
+                                }
+                                ConnectionWriteRoot::SubModulePort(port) => {
+                                    if let Some(span) = port.port_name_span {
+                                        todo!("Syntax highlight for named ports")
+                                    }
+                                }
+                            }
                         }
                         Instruction::SubModule(sm) => {
                             result.push((IDEIdentifierType::Interface, sm.module_name_span));

src/file_position.rs

@@ -1,5 +1,7 @@
 use std::{fmt::Display, ops::{Index, Range}};
 
+use crate::linker::FileUUID;
+
 // Span is defined as byte-byte idx. Start inclusive, end exclusive
 #[derive(Clone,Copy,Debug,PartialEq,Eq,Hash)]
 pub struct Span(usize, usize);
@@ -91,6 +93,9 @@ impl Ord for LineCol {
 }
 
 
+pub type SpanFile = (Span, FileUUID);
+
+
 pub struct FileText {
     pub file_text : String,
     lines_start_at : Vec<usize>

src/flattening/initialization.rs

@@ -46,7 +46,7 @@ pub struct ModulePorts {
 }
 
 impl ModulePorts {
-    const MAIN_INTERFACE_ID : InterfaceID = InterfaceID::from_hidden_value(0);
+    pub const MAIN_INTERFACE_ID : InterfaceID = InterfaceID::from_hidden_value(0);
 
     /// Get a port by the given name. Returns None if it does not exist
     pub fn get_port_by_name(&self, name : &str) -> Option<PortID> {