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Refactor latency counting to improve readability
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Now the latency algorithm first attempts to find the exact latencies of all inputs and outputs, and only afterwards fills in all internal latencies
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VonTum committed Feb 15, 2024
1 parent 3a4a5ac commit b31c76e
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Showing 5 changed files with 269 additions and 267 deletions.
4 changes: 2 additions & 2 deletions README.md
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Expand Up @@ -78,10 +78,10 @@ The main goals of the language are roughly listed below:
- [x] Indeterminable port latency
- [x] Latency Counting uses latency specifiers
- [x] Latency for output-only modules
- [ ] Latency Counting is invariant across arbitrary algorithm starting nodes
- [x] Latency Counting is invariant across arbitrary algorithm starting nodes
- [ ] Latency Counting for "disjoint Input-Output blocks"
- [ ] Integrate into Verilog generation
- [ ] Negative Registers
- [ ] Latency Offsets
- [ ] Latency Cuts

### LSP
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14 changes: 10 additions & 4 deletions multiply_add.sus
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Expand Up @@ -452,19 +452,19 @@ module undeteriminable_input_latency : int a, int b -> int x, int y {
y = t;
}

module determinable_input_latency : int a, int b -> int x, int y {
module specified_input_latency : int a'0, int b'1 -> int x, int y {
reg int a_d = a;
int t = a_d + b;
reg reg int a_dd = a;
reg reg reg int a_dd = a;
reg int t_d = t;
x = t_d + a_dd;
y = t;
}

module specified_input_latency : int a'0, int b'1 -> int x, int y {
module determinable_input_latency : int a, int b -> int x, int y {
reg int a_d = a;
int t = a_d + b;
reg reg reg int a_dd = a;
reg reg int a_dd = a;
reg int t_d = t;
x = t_d + a_dd;
y = t;
Expand All @@ -479,6 +479,12 @@ module determinable_because_no_input_output_ports : int a -> int x {
x = t_d + a_dd;
}

// This module is a copy of ::undeteriminable_input_latency, but it doesn't have an error, because we just assume the latency of the inner nodes to be the earliest possible.
module conflicting_latency_declarations : int a'1 -> int x'2 {
reg int nio = a;
reg x = nio;
}

module bad_cycle : int a -> int r {
state int test;
initial test = 0;
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2 changes: 1 addition & 1 deletion src/codegen_fallback.rs
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Expand Up @@ -6,7 +6,7 @@ fn get_type_name_size(id : TypeUUID) -> u64 {
if id == get_builtin_type("int") {
32 // TODO concrete int sizes
} else if id == get_builtin_type("bool") {
1 // TODO concrete int sizes
1
} else {
println!("TODO Named Structs Size");
1 // todo!() // Named structs are not implemented yet
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