Add port_map to FlattenedModule

pc2 · Apr 22, 2024 · 628f635 · 628f635
1 parent e5fc2bb
commit 628f635
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Showing 3 changed files with 34 additions and 7 deletions.
diff --git a/src/arena_alloc.rs b/src/arena_alloc.rs
@@ -390,6 +390,9 @@ impl<T, IndexMarker : UUIDMarker> FlatAlloc<T, IndexMarker> {
     pub fn new() -> Self {
         Self{data : Vec::new(), _ph : PhantomData}
     }
+    pub fn with_capacity(cap : usize) -> Self {
+        Self{data : Vec::with_capacity(cap), _ph : PhantomData}
+    }
     pub fn get_next_alloc_id(&self) -> UUID<IndexMarker> {
         let uuid = self.data.len();
         UUID(uuid, PhantomData)

diff --git a/src/flattening/mod.rs b/src/flattening/mod.rs
@@ -18,7 +18,7 @@ use crate::{
     value::Value
 };
 
-use self::{initialization::ModulePorts, name_context::LocalVariableContext};
+use self::{initialization::{ModulePorts, PortIDMarker}, name_context::LocalVariableContext};
 
 
 
@@ -128,11 +128,12 @@ pub type FlatIDRange = UUIDRange<FlatIDMarker>;
 #[derive(Debug)]
 pub enum ConnectionWritePathElement {
     ArrayIdx{idx : FlatID, bracket_span : BracketSpan},
-    //StructField(FieldID)
+    //ModulePort{id : PortID, name_span : Span}
 }
 #[derive(Debug)]
 pub enum ConnectionWritePathElementComputed {
-    ArrayIdx(usize)
+    ArrayIdx(usize),
+    //ModulePort(PortID)
 }
 
 // These are assignable connections
@@ -432,6 +433,7 @@ impl<'l, 'e> LocalOrGlobal<'l, 'e> {
 
 struct FlatteningContext<'l> {
     instructions : FlatAlloc<Instruction, FlatIDMarker>,
+    port_map : FlatAlloc<FlatID, PortIDMarker>,
     errors : ErrorCollector,
     is_declared_in_this_module : bool,
 
@@ -1019,7 +1021,9 @@ impl<'l> FlatteningContext<'l> {
 
     fn flatten_declaration_list(&mut self, identifier_type : IdentifierType, read_only : bool, ports : &mut Vec<FlatID>, cursor : &mut Cursor<'l>) {
         cursor.list(kind!("declaration_list"), |cursor| {
-            ports.push(self.flatten_declaration::<false, false>(identifier_type, read_only, true, cursor));
+            let id = self.flatten_declaration::<false, false>(identifier_type, read_only, true, cursor);
+            ports.push(id);
+            self.port_map.alloc(id);
         });
     }
 
@@ -1048,6 +1052,7 @@ impl<'l> FlatteningContext<'l> {
 
         let mut nested_context = FlatteningContext {
             instructions: std::mem::replace(&mut self.instructions, FlatAlloc::new()),
+            port_map: FlatAlloc::new(),
             errors: ErrorCollector::new(module.link_info.file, local_linker.file.file_text.len()), // Temporary ErrorCollector, unused
             is_declared_in_this_module: false,
             linker: local_linker,
@@ -1099,7 +1104,8 @@ pub struct FlattenedModule {
     pub instructions : FlatAlloc<Instruction, FlatIDMarker>,
     pub errors : ErrorCollector,
     pub interface_ports : InterfacePorts<FlatID>,
-    pub resolved_globals : ResolvedGlobals
+    pub resolved_globals : ResolvedGlobals,
+    pub port_map : FlatAlloc<FlatID, PortIDMarker>
 }
 
 impl FlattenedModule {
@@ -1108,7 +1114,8 @@ impl FlattenedModule {
             instructions : FlatAlloc::new(),
             errors,
             interface_ports : InterfacePorts::empty(),
-            resolved_globals : ResolvedGlobals::new()
+            resolved_globals : ResolvedGlobals::new(),
+            port_map : FlatAlloc::new()
         }
     }
 
@@ -1126,12 +1133,20 @@ impl FlattenedModule {
 
         let mut context = FlatteningContext{
             instructions : FlatAlloc::new(),
+            port_map : FlatAlloc::with_capacity(module.module_ports.ports.len()),
             errors : ErrorCollector::new(module.link_info.file, global_resolver.file.file_text.len()),
             is_declared_in_this_module : true,
             linker : global_resolver,
             local_variable_context : LocalVariableContext::new_initial()
         };
 
+        // Make sure that the gathered ports 
+        assert_eq!(module.module_ports.ports.len(), context.port_map.len());
+        for ((_, port), (_, id)) in zip(&module.module_ports.ports, &context.port_map) {
+            let name_span = context.instructions[*id].extract_wire_declaration().name_span;
+            assert_eq!(port.name_span, name_span);
+        }
+
         // Temporary, switch to iterating over nodes in file itself when needed. 
         let interface_ports = context.flatten_module(&mut cursor);
 
@@ -1140,6 +1155,7 @@ impl FlattenedModule {
             errors : context.errors,
             instructions : context.instructions,
             interface_ports,
+            port_map : context.port_map
         }
     }
 }
diff --git a/src/flattening/typechecking.rs b/src/flattening/typechecking.rs
@@ -1,14 +1,16 @@
-use crate::linker::ConstantUUIDMarker;
+use crate::linker::{ConstantUUIDMarker, ModuleUUIDMarker};
 
 use super::*;
 
 
 pub fn typecheck_all_modules(linker : &mut Linker) {
+    let linker_modules : *const ArenaAllocator<Module, ModuleUUIDMarker> = &linker.modules;
     for (_id, module) in &mut linker.modules {
         println!("Typechecking {}", &module.link_info.name);
         let mut context = TypeCheckingContext{
             instructions : &mut module.flattened.instructions,
             errors : &module.flattened.errors,
+            linker_modules,
             linker_types : &linker.types,
             linker_constants : &linker.constants
         };
@@ -24,6 +26,12 @@ struct TypeCheckingContext<'l, 'instr> {
     instructions : &'instr mut FlatAlloc<Instruction, FlatIDMarker>,
     errors : &'instr ErrorCollector,
 
+    /// A constant ptr to all modules. Accessing it requires an unsafe dereference. 
+    /// 
+    /// The Typechecking code cannot modify any of the fields it reads from other modules. 
+    /// 
+    /// It can only modify the fields it sets itself. These fields are [WireInstance::typ] and [WireInstance::is_compiletime]
+    linker_modules : *const ArenaAllocator<Module, ModuleUUIDMarker>,
     linker_types : &'l ArenaAllocator<NamedType, TypeUUIDMarker>,
     linker_constants : &'l ArenaAllocator<NamedConstant, ConstantUUIDMarker>
 }