Fix submodule ports must have exact latencies

README.md

@@ -1,7 +1,7 @@
 # SUS Language
 A Hardware Description Language focussed on strong type and temporal safety features
 
-Main Inspirations: TL-Verilog, Filament, Rust
+Main Inspirations: [TL-Verilog](https://arxiv.org/abs/1811.01780), [Filament](https://rachitnigam.com/files/pubs/filament.pdf), [Spade](https://spade-lang.org/), [Rust](https://www.rust-lang.org/)
 
 ## Core philosophy
 This project is an attempt to create a safety-first, correct-by-default HDL. It must make programming easier and safer without sacrificing on low level control. Much akin to what Rust is for the software industry. 
@@ -288,11 +288,12 @@ Constants specifically require that the modules the constant affect aren't being
 ### Temporal safety
 - Operations may only happen on data of the same 'time slice' within a stream
 - "Happens-before" relations -> proving FIFOs
+- LTL assertions of hardware
 
 ### Strong Typing
 - Actual data types
 - sized integers   (Min-max), not necessarily on power of 2 boundary
-- representation independent integers
+- representation independent integers?
 - Structs
 - Include Rust-style enum types?
 - operator overloading?

src/instantiation/mod.rs

@@ -521,19 +521,20 @@ impl<'fl, 'l> InstantiationContext<'fl, 'l> {
         Some(())
     }
 
-    // Computes all latencies involved
-    pub fn compute_latencies(&mut self, ports : &InterfacePorts<WireID>) -> Option<()> {
+    fn make_fanins(&self) -> (ListOfLists<FanInOut>, Vec<SpecifiedLatency>) {
         let mut fanins : ListOfLists<FanInOut> = ListOfLists::new_with_groups_capacity(self.wires.len());
+        let mut initial_latencies = Vec::new();
 
         // Wire to wire Fanin
-        let mut initial_latencies = Vec::new();
         for (id, wire) in &self.wires {
             fanins.new_group();
             wire.source.iter_sources_with_min_latency(&mut |from, delta_latency| {
                 fanins.push_to_last_group(FanInOut{other : from.get_hidden_value(), delta_latency});
             });
 
             // Submodules Fanin
+            // This creates two way connections, from any input i to output o it creates a |o| - |i| length connection, and a -(|o| - |i|) backward connection. This fixes them to be an exact latency apart. 
+            // This is O(lots) but doesn't matter, usually very few submodules. Fix this if needed
             for (_id, sub_mod) in &self.submodules {
                 for (self_output, submodule_output) in zip(sub_mod.wires.outputs(), sub_mod.instance.interface.outputs()) {
                     if *self_output != id {continue}
@@ -544,12 +545,29 @@ impl<'fl, 'l> InstantiationContext<'fl, 'l> {
                         fanins.push_to_last_group(FanInOut{other: self_input.get_hidden_value(), delta_latency});
                     }
                 }
+                // Also have to add inverse connections, such that the ports of the module are well and truly fixed together
+                for (self_input, submodule_input) in zip(sub_mod.wires.inputs(), sub_mod.instance.interface.inputs()) {
+                    if *self_input != id {continue}
+                    for (self_output, submodule_output) in zip(sub_mod.wires.outputs(), sub_mod.instance.interface.outputs()) {
+
+                        let delta_latency = sub_mod.instance.wires[*submodule_output].absolute_latency - sub_mod.instance.wires[*submodule_input].absolute_latency;
+
+                        fanins.push_to_last_group(FanInOut{other: self_output.get_hidden_value(), delta_latency : -delta_latency});
+                    }
+                }
             }
 
             if wire.absolute_latency != CALCULATE_LATENCY_LATER {
                 initial_latencies.push(SpecifiedLatency { wire: id.get_hidden_value(), latency: wire.absolute_latency })
             }
         }
+
+        (fanins, initial_latencies)
+    }
+
+    // Computes all latencies involved
+    pub fn compute_latencies(&mut self, ports : &InterfacePorts<WireID>) -> Option<()> {
+        let (fanins, initial_latencies) = self.make_fanins();
 
         // Process fanouts
         let fanouts = convert_fanin_to_fanout(&fanins);