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Split Type into Span holding and not Span holding
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VonTum committed Feb 5, 2024
1 parent 9a75cf4 commit 4c19816
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Showing 7 changed files with 205 additions and 174 deletions.
9 changes: 8 additions & 1 deletion src/ast.rs
Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,13 @@ impl Span {
pub fn whole_file_span(tokens : &TokenizeResult) -> Span {
Span(0, tokens.token_types.len())
}
pub fn contains_token(&self, token_idx : usize) -> bool {
self.0 >= token_idx && self.1 <= token_idx
}
// Not really a useful quantity. Should only be used comparatively, find which is the nested-most span
pub fn size(&self) -> usize {
self.1 - self.0
}
#[track_caller]
pub fn assert_is_single_token(&self) -> usize {
assert!(self.1 == self.0, "Span is not singleton! {}..{}", self.0, self.1);
Expand Down Expand Up @@ -242,7 +249,7 @@ impl Module {
println!(" {port_direction} {port_name} -> {:?}", port);
}
println!("Instantiations:");
for (id, inst) in &self.flattened.instantiations {
for (id, inst) in &self.flattened.instructions {
println!(" {:?}: {:?}", id, inst);
}
}
Expand Down
4 changes: 2 additions & 2 deletions src/codegen_fallback.rs
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
use std::{iter::zip, ops::Deref};

use crate::{ast::{Module, IdentifierType}, instantiation::{ConnectToPathElem, InstantiatedModule, RealWireDataSource}, linker::{get_builtin_type, TypeUUID}, typing::ConcreteType, tokenizer::get_token_type_name, flattening::Instantiation, value::Value};
use crate::{ast::{Module, IdentifierType}, instantiation::{ConnectToPathElem, InstantiatedModule, RealWireDataSource}, linker::{get_builtin_type, TypeUUID}, typing::ConcreteType, tokenizer::get_token_type_name, flattening::Instruction, value::Value};

fn get_type_name_size(id : TypeUUID) -> u64 {
if id == get_builtin_type("int") {
Expand Down Expand Up @@ -82,7 +82,7 @@ pub fn gen_verilog_code(md : &Module, instance : &InstantiatedModule) -> String
program_text.push_str(");\n");

for (_id, w) in &instance.wires {
if let Instantiation::Declaration(wire_decl) = &md.flattened.instantiations[w.original_wire] {
if let Instruction::Declaration(wire_decl) = &md.flattened.instructions[w.original_wire] {
// Don't print named inputs and outputs, already did that in interface
match wire_decl.identifier_type {
IdentifierType::Input | IdentifierType::Output => {continue;}
Expand Down
22 changes: 11 additions & 11 deletions src/dev_aid/syntax_highlighting.rs
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@

use std::{ops::Range, path::PathBuf};

use crate::{ast::*, tokenizer::*, parser::*, linker::{FileData, Linker, FileUUIDMarker, FileUUID, NameElem}, arena_alloc::ArenaVector, flattening::{Instantiation, WireSource}};
use crate::{ast::*, tokenizer::*, parser::*, linker::{FileData, Linker, FileUUIDMarker, FileUUID, NameElem}, arena_alloc::ArenaVector, flattening::{Instruction, WireSource}};

use ariadne::FileCache;
use console::Style;
Expand Down Expand Up @@ -113,12 +113,12 @@ fn walk_name_color(all_objects : &[NameElem], linker : &Linker, result : &mut [I
let (ide_typ, link_info) = match obj_uuid {
NameElem::Module(id) => {
let module = &linker.modules[*id];
for (_id, item) in &module.flattened.instantiations {
for (_id, item) in &module.flattened.instructions {
match item {
Instantiation::Wire(w) => {
Instruction::Wire(w) => {
match &w.source {
&WireSource::WireRead(from_wire) => {
let decl = module.flattened.instantiations[from_wire].extract_wire_declaration();
let decl = module.flattened.instructions[from_wire].extract_wire_declaration();
if !decl.is_declared_in_this_module {continue;} // Virtual wires don't appear in this program text
result[w.span.assert_is_single_token()].typ = IDETokenType::Identifier(IDEIdentifierType::Value(decl.identifier_type));
}
Expand All @@ -131,22 +131,22 @@ fn walk_name_color(all_objects : &[NameElem], linker : &Linker, result : &mut [I
}
}
}
Instantiation::Declaration(decl) => {
Instruction::Declaration(decl) => {
if !decl.is_declared_in_this_module {continue;} // Virtual wires don't appear in this program text
result[decl.name_token].typ = IDETokenType::Identifier(IDEIdentifierType::Value(decl.identifier_type));
decl.typ.for_each_located_type(&mut |_, span| {
decl.typ_expr.for_each_located_type(&mut |_, span| {
set_span_name_color(span, IDEIdentifierType::Type, result);
});
}
Instantiation::Write(conn) => {
let decl = module.flattened.instantiations[conn.to.root].extract_wire_declaration();
Instruction::Write(conn) => {
let decl = module.flattened.instructions[conn.to.root].extract_wire_declaration();
if !decl.is_declared_in_this_module {continue;} // Virtual wires don't appear in this program text
result[conn.to.span.0].typ = IDETokenType::Identifier(IDEIdentifierType::Value(decl.identifier_type));
}
Instantiation::SubModule(sm) => {
set_span_name_color(sm.typ_span, IDEIdentifierType::Interface, result);
Instruction::SubModule(sm) => {
set_span_name_color(sm.module_name_span, IDEIdentifierType::Interface, result);
}
Instantiation::IfStatement(_) | Instantiation::ForStatement(_) => {}
Instruction::IfStatement(_) | Instruction::ForStatement(_) => {}
}
}
(IDEIdentifierType::Interface, &module.link_info)
Expand Down
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