Pr 43 build a complete qick testbench to run simulations

firmware/hdl/fifo_dc_axi_xpm.sv

@@ -462,4 +462,4 @@ module fifo_dc_axi_xpm
 
    // End of xpm_fifo_async_inst instantiation
 
-endmodule;
+endmodule

firmware/testbench/qick_testbench/qick_testbench.xpr

@@ -61,7 +61,7 @@
     <Option Name="UseIPStaticLibs" Val="0"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="zcu216"/>
-    <Option Name="WTXSimLaunchSim" Val="836"/>
+    <Option Name="WTXSimLaunchSim" Val="910"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -655,6 +655,20 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PPRDIR/src/tb/qick_dut.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/src/tb/model_DAC_ADC.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="tb_qick"/>
@@ -669,7 +683,6 @@
         <Option Name="PamPseudoTop" Val="pseudo_tb"/>
         <Option Name="SrcSet" Val="sources_1"/>
         <Option Name="XSimWcfgFile" Val="$PPRDIR/src/tb/tb_qick_behav.wcfg"/>
-        <Option Name="xsim.simulate.log_all_signals" Val="true"/>
       </Config>
     </FileSet>
     <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
@@ -703,7 +716,9 @@
   <Runs Version="1" Minor="20">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xczu49dr-ffvf1760-2-e" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
@@ -712,7 +727,9 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xczu49dr-ffvf1760-2-e" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>

firmware/testbench/qick_testbench/src/tb/model_DAC_ADC.sv

@@ -0,0 +1,87 @@
+///////////////////////////////////////////////////////////////////////////////
+//  Fermilab National Accelerator Laboratory
+///////////////////////////////////////////////////////////////////////////////
+// Description: 
+// DAC-ADC RF frontend model
+///////////////////////////////////////////////////////////////////////////
+
+module model_DAC_ADC #(
+   parameter integer DAC_W = 16,
+   parameter integer ADC_W = 16,
+   parameter integer BUFFER_SIZE = 16
+)(
+   input wire clk_DAC,
+   input wire [DAC_W-1:0] dac_sample,
+
+   input wire clk_ADC,
+   output logic [ADC_W-1:0] adc_sample,
+
+   input int mode  // 0 = ZOH, 1 = linear
+);
+
+   // Parameters
+   real pi = 3.14159265358979;
+
+   // DAC samples Buffer
+   real buffer_samples[BUFFER_SIZE];
+   real buffer_times[BUFFER_SIZE];
+   int wr_ptr = 0;
+
+   // Internal Signals
+   real signal_in;
+   real sampled_ADC;
+
+   initial begin
+      for (int i=0; i<BUFFER_SIZE; i++) begin
+         buffer_samples[i] = 0.0;
+         buffer_times[i] = 0.0;
+      end
+   end
+
+   // DAC processing
+   always @(posedge clk_DAC) begin
+      real t_now = $realtime * 1e-9;
+      signal_in = $signed(dac_sample) / 2.0**(DAC_W-1);
+
+      buffer_samples[wr_ptr] = signal_in;
+      buffer_times[wr_ptr] = t_now;
+      wr_ptr = (wr_ptr + 1) % BUFFER_SIZE;
+
+      // $display("[%0t ns] DAC sample: %f", $time, signal_in);
+   end
+
+   // ADC processing
+   always @(posedge clk_ADC) begin
+      real t_adc = $realtime * 1e-9;
+      real val;
+      case (mode)
+         0: begin
+               // ZOH: last value
+               int idx_last = (wr_ptr + BUFFER_SIZE - 1) % BUFFER_SIZE;
+               val = buffer_samples[idx_last];
+         end
+         1: begin
+               // Linear: use last 2 samples to interpolate
+               int idx_curr = (wr_ptr + BUFFER_SIZE - 1) % BUFFER_SIZE;
+               int idx_prev = (wr_ptr + BUFFER_SIZE - 2) % BUFFER_SIZE;
+               real t1 = buffer_times[idx_prev];
+               real t2 = buffer_times[idx_curr];
+               real y1 = buffer_samples[idx_prev];
+               real y2 = buffer_samples[idx_curr];
+               if (t2 != t1)
+                  val = y1 + (t_adc - t1) * (y2 - y1)/(t2 - t1);
+               else
+                  val = y2;
+         end
+         default: val = 0.0;
+      endcase
+
+      if (val > 1.0)          sampled_ADC = 1.0;
+      else if (val < -1.0)    sampled_ADC = -1.0;
+      else                    sampled_ADC = val;
+      adc_sample = sampled_ADC * $signed(2**(ADC_W-1)-1);
+
+      // $display("[%0t ns] ADC sample (mode %0d): %f", $time, mode, sampled_ADC);
+   end
+
+endmodule