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4 changes: 2 additions & 2 deletions doc/01_specification/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -253,8 +253,8 @@ Operating modes (Privilege Levels)
+--------+--------------------------------------------------------------+
| PVL-30 | CV32E20 shall export the CPU's operating mode as an address |
| | phase attribute output signals on the Harvard memory |
| | interfaces (instruction fetch, data load/store) with machine |
| | mode defined as 1'b1 and user mode as 1'b0. |
| | interfaces (instruction fetch, data load/store) with mode |
| | encoded as per specification in [RVpriv]_. |
+--------+--------------------------------------------------------------+
| PVL-40 | CV32E20 shall support the **bare** (addressing) mode, that |
| | is, no support for address translation or protection. |
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5 changes: 4 additions & 1 deletion rtl/cve2_core.sv
Original file line number Diff line number Diff line change
Expand Up @@ -103,7 +103,8 @@ module cve2_core import cve2_pkg::*; #(

// CPU Control Signals
input logic fetch_enable_i,
output logic core_busy_o
output logic core_busy_o,
priv_lvl_e priv_mode_o
);

localparam int unsigned PMP_NUM_CHAN = 3;
Expand Down Expand Up @@ -280,6 +281,8 @@ module cve2_core import cve2_pkg::*; #(
// interfaces to finish ongoing operations.
assign core_busy_o = ctrl_busy | if_busy | lsu_busy;

assign priv_mode_o = priv_mode_id;

//////////////
// IF stage //
//////////////
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6 changes: 4 additions & 2 deletions rtl/cve2_top.sv
Original file line number Diff line number Diff line change
Expand Up @@ -95,7 +95,8 @@ module cve2_top import cve2_pkg::*; #(

// CPU Control Signals
input logic fetch_enable_i,
output logic core_sleep_o
output logic core_sleep_o,
priv_lvl_e priv_mode_o
);

// Scrambling Parameter
Expand Down Expand Up @@ -228,7 +229,8 @@ module cve2_top import cve2_pkg::*; #(
`endif

.fetch_enable_i (fetch_enable_q),
.core_busy_o (core_busy_d)
.core_busy_o (core_busy_d),
.priv_mode_o
);

////////////////////////
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