chore(deps): update chiselversion to v6.6.0

[renovate]

This PR contains the following updates:

Package	Update	Change
org.chipsalliance:chisel (source)	minor	6.5.0 -> 6.6.0
org.chipsalliance:chisel-plugin (source)	minor	6.5.0 -> 6.6.0

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Release Notes

chipsalliance/chisel (org.chipsalliance:chisel)

v6.6.0: Chisel v6.6.0

Compare Source

Features

• Implement Lookupable for HasTarget (used by SRAM) (backport #​4481) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/44822)
• Allow BoringUtils to use existing port in a closed module (backport #​4484) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/44866)
  When trying to drill a port, it doesn't matter if the module is closed. We do not need to construct new hardware and can just use the existing port.
• Implement Lookupable for Unit (backport #​4497) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/44988)

API Modification

• Deprecate all Injecting Aspect Code (backport #​4415) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/44166)

API Deprecation

• Deprecate more Aspect parts (backport #​4420) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/44211)

Fixes

• Remove unnecessary overrides of lref and ref in Property (backport #​4309) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/43100)
  This fixes an issue with views of List of Property.
• Improve error messages for empty Mux1H and PriorityMux (backport #​4391) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/43933)
• Handle define on views of Probes (backport #​4308) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/43111)
• Support BoringUtils.bore on OpaqueType wrapping a Property. (backport #​4337) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/43388)
  This ensures boring from an OpaqueType that wraps a Property uses the correct connection operator in the IR.
• Make it legal to extract zero bits from a zero-width UInt (backport #​4445) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/44477)
• Fix Arg.name and earlyLocalName for probes (backport #​4359) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/43600)
• Fix Boring.rwTap on instance ports (backport #​4451) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/44522)
  BoringUtils.rwTap can now works on a port of an instance: Instance[..]
• Fix Select.attachedTo (backport #​4458) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/44611)
• Fix missing string interpolators, add -Xlint:missing-interpolator (backport #​4471) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/44733)
• Add Probes to .toString Data methods (backport #​4478) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/44800)
  Probe chisel types now include the kind of probe and layer in their .toString method

Documentation

• Improve the error message for mismatched types in Mux (backport #​4331) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/43322)

Dependency Updates

• [6.x] Bump to CIRCT 1.62.1 (by @​jackkoenig in https://github.com/chipsalliance/chisel/pull/4387)
  • [FIRRTL] LowerToHW: guard against folded operations https://github.com/llvm/circt/pull/73588)
• Add Scala 2.13.15 to compiler plugin cross-build (backport #​4410) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/44133)
  Add support for Scala 2.13.15

Build and Internal Changes

• Add permissions to website deployment job (backport #​4285) (by @​mergify[bot] inhttps://github.com/chipsalliance/chisel/pull/42900)
• [6.x] Enable MiMa for v6.5.0 (by @​chiselbot in https://github.com/chipsalliance/chisel/pull/4279)

Full Changelog: chipsalliance/chisel@v6.5.0...v6.6.0

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