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Merge pull request #5 from Architeuthis-Flux/main
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Fixed names to match the newly canonized versions
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@nilclass
nilclass authored Feb 9, 2024
2 parents ade3078 + a77f9b5 commit 73a1ee7
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Showing 4 changed files with 133 additions and 91 deletions.
5 changes: 4 additions & 1 deletion src/device_manager.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -122,7 +122,10 @@ impl DeviceManager {
unreachable!()
};

if (*vid, *pid) == (0x1d50, 0xACAB) || (*vid, *pid) == (0xACAB, 0x1312) || (*vid, *pid) == (0x1209, 0xACAB) {
if (*vid, *pid) == (0x1d50, 0xACAB)
|| (*vid, *pid) == (0xACAB, 0x1312)
|| (*vid, *pid) == (0x1209, 0xACAB)
{
//it's now matching based on PID, which I have changed, so update your firmware
// remove "tty" ports on Mac OS (only use the "cu" ones)
fixup_mac_ports(infos);
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12 changes: 6 additions & 6 deletions src/parser.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -220,9 +220,9 @@ mod tests {
(GND, Column(32)),
(SUPPLY_5V, Column(7)),
(SUPPLY_5V, Column(15)),
(SUPPLY_5V, A7),
(SUPPLY_5V, NANO_A7),
(SUPPLY_3V3, Column(55)),
(SUPPLY_3V3, A4),
(SUPPLY_3V3, NANO_A4),
(Column(27), Column(8)),
(Column(27), Column(11)),
(Column(27), Column(20)),
Expand Down Expand Up @@ -287,7 +287,7 @@ mod tests {
Message::Net(Net {
index: 4,
number: 4,
nodes: vec![Node::DAC0_5V],
nodes: vec![Node::DAC0],
special: true,
color: Color([0x23, 0x11, 0x11]),
machine: false,
Expand All @@ -296,7 +296,7 @@ mod tests {
Message::Net(Net {
index: 5,
number: 5,
nodes: vec![Node::DAC1_8V],
nodes: vec![Node::DAC1],
special: true,
color: Color([0x23, 0x09, 0x13]),
machine: false,
Expand All @@ -305,7 +305,7 @@ mod tests {
Message::Net(Net {
index: 6,
number: 6,
nodes: vec![Node::I_P],
nodes: vec![Node::ISENSE_PLUS],
special: true,
color: Color([0x23, 0x23, 0x23]),
machine: false,
Expand All @@ -314,7 +314,7 @@ mod tests {
Message::Net(Net {
index: 7,
number: 7,
nodes: vec![Node::I_N],
nodes: vec![Node::ISENSE_MINUS],
special: true,
color: Color([0x23, 0x23, 0x23]),
machine: false,
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199 changes: 119 additions & 80 deletions src/types.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -185,41 +185,41 @@ pub enum Node {
GND,
SUPPLY_5V,
SUPPLY_3V3,
DAC0_5V,
DAC1_8V,
I_N,
I_P,
ADC0_5V,
ADC1_5V,
ADC2_5V,
ADC3_8V,
D0,
D1,
D2,
D3,
D4,
D5,
D6,
D7,
D8,
D9,
D10,
D11,
D12,
D13,
A0,
A1,
A2,
A3,
A4,
A5,
A6,
A7,
RESET,
AREF,
GPIO_0,
UART_Rx,
UART_Tx,
DAC0,
DAC1,
ISENSE_MINUS,
ISENSE_PLUS,
ADC0,
ADC1,
ADC2,
ADC3,
NANO_D0,
NANO_D1,
NANO_D2,
NANO_D3,
NANO_D4,
NANO_D5,
NANO_D6,
NANO_D7,
NANO_D8,
NANO_D9,
NANO_D10,
NANO_D11,
NANO_D12,
NANO_D13,
NANO_A0,
NANO_A1,
NANO_A2,
NANO_A3,
NANO_A4,
NANO_A5,
NANO_A6,
NANO_A7,
NANO_RESET,
NANO_AREF,
RP_GPIO_0,
RP_UART_Rx,
RP_UART_Tx,
Column(u8),
}

Expand All @@ -239,59 +239,98 @@ impl Node {
} else {
use Node::*;
match s {
// these are the canonical names
"GND" => Ok(GND),
"SUPPLY_5V" => Ok(SUPPLY_5V),
"SUPPLY_3V3" => Ok(SUPPLY_3V3),
"DAC0_5V" => Ok(DAC0_5V),
"DAC1_8V" => Ok(DAC1_8V),
"I_N" => Ok(I_N),
"I_P" => Ok(I_P),
"ADC0_5V" => Ok(ADC0_5V),
"ADC1_5V" => Ok(ADC1_5V),
"ADC2_5V" => Ok(ADC2_5V),
"ADC3_8V" => Ok(ADC3_8V),
"D0" => Ok(D0),
"D1" => Ok(D1),
"D2" => Ok(D2),
"D3" => Ok(D3),
"D4" => Ok(D4),
"D5" => Ok(D5),
"D6" => Ok(D6),
"D7" => Ok(D7),
"D8" => Ok(D8),
"D9" => Ok(D9),
"D10" => Ok(D10),
"D11" => Ok(D11),
"D12" => Ok(D12),
"D13" => Ok(D13),
"A0" => Ok(A0),
"A1" => Ok(A1),
"A2" => Ok(A2),
"A3" => Ok(A3),
"A4" => Ok(A4),
"A5" => Ok(A5),
"A6" => Ok(A6),
"A7" => Ok(A7),
"RESET" => Ok(RESET),
"AREF" => Ok(AREF),
"GPIO_0" => Ok(GPIO_0),
"UART_Rx" => Ok(UART_Rx),
"UART_Tx" => Ok(UART_Tx),
"DAC0" => Ok(DAC0),
"DAC1" => Ok(DAC1),
"ISENSE_MINUS" => Ok(ISENSE_MINUS),
"ISENSE_PLUS" => Ok(ISENSE_PLUS),
"ADC0" => Ok(ADC0),
"ADC1" => Ok(ADC1),
"ADC2" => Ok(ADC2),
"ADC3" => Ok(ADC3),
"NANO_D0" => Ok(NANO_D0),
"NANO_D1" => Ok(NANO_D1),
"NANO_D2" => Ok(NANO_D2),
"NANO_D3" => Ok(NANO_D3),
"NANO_D4" => Ok(NANO_D4),
"NANO_D5" => Ok(NANO_D5),
"NANO_D6" => Ok(NANO_D6),
"NANO_D7" => Ok(NANO_D7),
"NANO_D8" => Ok(NANO_D8),
"NANO_D9" => Ok(NANO_D9),
"NANO_D10" => Ok(NANO_D10),
"NANO_D11" => Ok(NANO_D11),
"NANO_D12" => Ok(NANO_D12),
"NANO_D13" => Ok(NANO_D13),
"NANO_A0" => Ok(NANO_A0),
"NANO_A1" => Ok(NANO_A1),
"NANO_A2" => Ok(NANO_A2),
"NANO_A3" => Ok(NANO_A3),
"NANO_A4" => Ok(NANO_A4),
"NANO_A5" => Ok(NANO_A5),
"NANO_A6" => Ok(NANO_A6),
"NANO_A7" => Ok(NANO_A7),
"NANO_RESET" => Ok(NANO_RESET),
"NANO_AREF" => Ok(NANO_AREF),
"RP_GPIO_0" => Ok(RP_GPIO_0),
"RP_UART_Rx" => Ok(RP_UART_Rx),
"RP_UART_Tx" => Ok(RP_UART_Tx),

// ALIASES: these are names used for the nodes in the netlist output.
// They are not supported as input for nodefiles.
"5V" => Ok(SUPPLY_5V),
"3V3" => Ok(SUPPLY_3V3),
"DAC_0" => Ok(DAC0_5V),
"DAC_1" => Ok(DAC1_8V),
"I_NEG" => Ok(I_N),
"I_POS" => Ok(I_P),
"ADC_0" => Ok(ADC0_5V),
"ADC_1" => Ok(ADC1_5V),
"ADC_2" => Ok(ADC2_5V),
"ADC_3" => Ok(ADC3_8V),
"GPIO_16" => Ok(UART_Rx),
"GPIO_17" => Ok(UART_Tx),
"DAC0_5V" => Ok(DAC0),
"DAC1_8V" => Ok(DAC1),
"I_N" => Ok(ISENSE_MINUS),
"I_P" => Ok(ISENSE_PLUS),
"ADC0_5V" => Ok(ADC0),
"ADC1_5V" => Ok(ADC1),
"ADC2_5V" => Ok(ADC2),
"ADC3_8V" => Ok(ADC3),
"D0" => Ok(NANO_D0),
"D1" => Ok(NANO_D1),
"D2" => Ok(NANO_D2),
"D3" => Ok(NANO_D3),
"D4" => Ok(NANO_D4),
"D5" => Ok(NANO_D5),
"D6" => Ok(NANO_D6),
"D7" => Ok(NANO_D7),
"D8" => Ok(NANO_D8),
"D9" => Ok(NANO_D9),
"D10" => Ok(NANO_D10),
"D11" => Ok(NANO_D11),
"D12" => Ok(NANO_D12),
"D13" => Ok(NANO_D13),
"A0" => Ok(NANO_A0),
"A1" => Ok(NANO_A1),
"A2" => Ok(NANO_A2),
"A3" => Ok(NANO_A3),
"A4" => Ok(NANO_A4),
"A5" => Ok(NANO_A5),
"A6" => Ok(NANO_A6),
"A7" => Ok(NANO_A7),
"RESET" => Ok(NANO_RESET),
"AREF" => Ok(NANO_AREF),
"GPIO_0" => Ok(RP_GPIO_0),
"UART_Rx" => Ok(RP_UART_Rx),
"UART_Tx" => Ok(RP_UART_Tx),

"DAC 0" => Ok(DAC0),
"DAC 1" => Ok(DAC1),
"DAC_0" => Ok(DAC0),
"DAC_1" => Ok(DAC1),
"I_NEG" => Ok(ISENSE_MINUS),
"I_POS" => Ok(ISENSE_PLUS),
"ADC_0" => Ok(ADC0),
"ADC_1" => Ok(ADC1),
"ADC_2" => Ok(ADC2),
"ADC_3" => Ok(ADC3),
"GPIO_16" => Ok(RP_UART_Rx),
"GPIO_17" => Ok(RP_UART_Tx),

_ => Err(anyhow::anyhow!("Unknown node: {}", s)),
}
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8 changes: 4 additions & 4 deletions src/validate.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -6,10 +6,10 @@ const SPECIAL_NETS: [(u8, &str, Node); 7] = [
(1, "GND", Node::GND),
(2, "+5V", Node::SUPPLY_5V),
(3, "+3.3V", Node::SUPPLY_3V3),
(4, "DAC 0", Node::DAC0_5V),
(5, "DAC 1", Node::DAC1_8V),
(6, "I Sense +", Node::I_P),
(7, "I Sense -", Node::I_N),
(4, "DAC 0", Node::DAC0),
(5, "DAC 1", Node::DAC1),
(6, "I Sense +", Node::ISENSE_PLUS),
(7, "I Sense -", Node::ISENSE_MINUS),
];

pub fn netlist(netlist: Vec<Net>) -> anyhow::Result<Vec<Net>> {
Expand Down

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