Si5351C PLL denominator packing and PLLB feedback divider #390

Denominator. In ConfigureClocks the MSNx_P3 bytes are merged with |=:

m_newConfiguration[addr + 1] |= MSNx_P3;
m_newConfiguration[addr] |= MSNx_P3 >> 8;

while every other multisynth register in the function is assigned with =. For PLLA addr is 26 and Reset() initializes register 27 to 0x80 from the defaults, so the programmed fractional denominator is P3 OR'ed with 0x80 on the first call and with the previous configuration's P3 on every later call.

PLLB. FindVCO computes plls[1].feedbackDivider = bestVCOB / plls[0].inputFreqHz - PLLA's input frequency - although SetPLL lets each PLL have its own input frequency and clock source.

ADF4002. CalculateRN stores the R/N counters without validating them against the 14-bit R and 13-bit N register fields. In MakeData the N MSB byte is OR'ed into register 0x05 together with cmbCPG << 5, so an N above 8191 does not merely truncate: bit 5 of N >> 8 lands on the charge-pump gain bit and higher bits on reserved/test bits.