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modm update bot
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Update STM32H5 headers to v1.4.0
1 parent 9ad4b52 commit b7da576

9 files changed

+94
-63
lines changed

‎README.md

+1-1
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ as the Cube release version in braces:
2323
- [C0: v1.3.0 created 30-October-2024](https://github.com/STMicroelectronics/STM32CubeC0)
2424
- [G0: v1.4.4 created 15-December-2023](https://github.com/STMicroelectronics/STM32CubeG0)
2525
- [G4: v1.2.5 created 25-September-2024](https://github.com/STMicroelectronics/STM32CubeG4)
26-
- [H5: v1.3.1 created 30-October-2024](https://github.com/STMicroelectronics/STM32CubeH5)
26+
- [H5: v1.4.0 created 05-February-2025](https://github.com/STMicroelectronics/STM32CubeH5)
2727
- [H7: v1.10.6 created 06-December-2024](https://github.com/STMicroelectronics/STM32CubeH7)
2828
- [WB: v1.12.2 created 05-June-2024](https://github.com/STMicroelectronics/STM32CubeWB)
2929
- [WBA: v1.5.0 created 22-October-2024](https://github.com/STMicroelectronics/STM32CubeWBA)

‎stm32h5xx/Include/stm32h503xx.h

+3-8
Original file line numberDiff line numberDiff line change
@@ -210,11 +210,6 @@ typedef struct
210210
uint32_t RESERVED2; /*!< Reserved, 0x0C */
211211
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
212212
__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
213-
uint32_t RESERVED3[246]; /*!< Reserved, */
214-
__IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */
215-
__IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */
216-
__IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */
217-
__IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */
218213
} CRC_TypeDef;
219214

220215
/**
@@ -2480,7 +2475,7 @@ typedef struct
24802475
#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
24812476
#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
24822477
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
2483-
#define ADC_AWD3CR_AWD2CH_19 (0x80000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00080000 */
2478+
#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
24842479

24852480
/******************** Bit definition for ADC_DIFSEL register ****************/
24862481
#define ADC_DIFSEL_DIFSEL_Pos (0U)
@@ -6456,7 +6451,7 @@ typedef struct
64566451
#define GPIO_HSLVR_HSLV10_Msk (0x1UL << GPIO_HSLVR_HSLV10_Pos) /*!< 0x00000400 */
64576452
#define GPIO_HSLVR_HSLV10 GPIO_HSLVR_HSLV10_Msk
64586453
#define GPIO_HSLVR_HSLV11_Pos (11U)
6459-
#define GPIO_HSLVR_HSLV11_Msk (x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */
6454+
#define GPIO_HSLVR_HSLV11_Msk (0x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */
64606455
#define GPIO_HSLVR_HSLV11 GPIO_HSLVR_HSLV11_Msk
64616456
#define GPIO_HSLVR_HSLV12_Pos (12U)
64626457
#define GPIO_HSLVR_HSLV12_Msk (0x1UL << GPIO_HSLVR_HSLV12_Pos) /*!< 0x00001000 */
@@ -6506,7 +6501,7 @@ typedef struct
65066501
#define GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) /*!< 0x00000400 */
65076502
#define GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk
65086503
#define GPIO_SECCFGR_SEC11_Pos (11U)
6509-
#define GPIO_SECCFGR_SEC11_Msk (x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */
6504+
#define GPIO_SECCFGR_SEC11_Msk (0x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */
65106505
#define GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk
65116506
#define GPIO_SECCFGR_SEC12_Pos (12U)
65126507
#define GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) /*!< 0x00001000 */

‎stm32h5xx/Include/stm32h523xx.h

+21-10
Original file line numberDiff line numberDiff line change
@@ -239,11 +239,6 @@ typedef struct
239239
uint32_t RESERVED2; /*!< Reserved, 0x0C */
240240
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
241241
__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
242-
uint32_t RESERVED3[246]; /*!< Reserved, */
243-
__IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */
244-
__IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */
245-
__IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */
246-
__IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */
247242
} CRC_TypeDef;
248243

249244
/**
@@ -814,6 +809,8 @@ typedef struct
814809

815810
typedef XSPI_TypeDef OCTOSPI_TypeDef;
816811

812+
813+
817814
/**
818815
* @brief Power Control
819816
*/
@@ -3706,7 +3703,7 @@ typedef struct
37063703
#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
37073704
#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
37083705
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
3709-
#define ADC_AWD3CR_AWD2CH_19 (0x80000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00080000 */
3706+
#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
37103707

37113708
/******************** Bit definition for ADC_DIFSEL register ****************/
37123709
#define ADC_DIFSEL_DIFSEL_Pos (0U)
@@ -3896,7 +3893,6 @@ typedef struct
38963893
#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
38973894

38983895

3899-
39003896
/******************************************************************************/
39013897
/* */
39023898
/* CRC calculation unit */
@@ -8001,6 +7997,7 @@ typedef struct
80017997
#define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
80027998
#define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
80037999

8000+
80048001
/******************************************************************************/
80058002
/* */
80068003
/* General Purpose IOs (GPIO) */
@@ -8754,7 +8751,7 @@ typedef struct
87548751
#define GPIO_HSLVR_HSLV10_Msk (0x1UL << GPIO_HSLVR_HSLV10_Pos) /*!< 0x00000400 */
87558752
#define GPIO_HSLVR_HSLV10 GPIO_HSLVR_HSLV10_Msk
87568753
#define GPIO_HSLVR_HSLV11_Pos (11U)
8757-
#define GPIO_HSLVR_HSLV11_Msk (x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */
8754+
#define GPIO_HSLVR_HSLV11_Msk (0x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */
87588755
#define GPIO_HSLVR_HSLV11 GPIO_HSLVR_HSLV11_Msk
87598756
#define GPIO_HSLVR_HSLV12_Pos (12U)
87608757
#define GPIO_HSLVR_HSLV12_Msk (0x1UL << GPIO_HSLVR_HSLV12_Pos) /*!< 0x00001000 */
@@ -8804,7 +8801,7 @@ typedef struct
88048801
#define GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) /*!< 0x00000400 */
88058802
#define GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk
88068803
#define GPIO_SECCFGR_SEC11_Pos (11U)
8807-
#define GPIO_SECCFGR_SEC11_Msk (x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */
8804+
#define GPIO_SECCFGR_SEC11_Msk (0x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */
88088805
#define GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk
88098806
#define GPIO_SECCFGR_SEC12_Pos (12U)
88108807
#define GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) /*!< 0x00001000 */
@@ -13477,6 +13474,9 @@ typedef struct
1347713474
#define RCC_AHB2LPENR_RNGLPEN_Pos (18U)
1347813475
#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00040000 */
1347913476
#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
13477+
#define RCC_AHB2LPENR_PKALPEN_Pos (19U)
13478+
#define RCC_AHB2LPENR_PKALPEN_Msk (0x1UL << RCC_AHB2LPENR_PKALPEN_Pos) /*!< 0x00080000 */
13479+
#define RCC_AHB2LPENR_PKALPEN RCC_AHB2LPENR_PKALPEN_Msk
1348013480
#define RCC_AHB2LPENR_SRAM2LPEN_Pos (30U)
1348113481
#define RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */
1348213482
#define RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk
@@ -15830,6 +15830,8 @@ typedef struct
1583015830
#define GTZC_CFGR3_HASH_Msk (0x01UL << GTZC_CFGR3_HASH_Pos)
1583115831
#define GTZC_CFGR3_RNG_Pos (18U)
1583215832
#define GTZC_CFGR3_RNG_Msk (0x01UL << GTZC_CFGR3_RNG_Pos)
15833+
#define GTZC_CFGR3_PKA_Pos (20U)
15834+
#define GTZC_CFGR3_PKA_Msk (0x01UL << GTZC_CFGR3_PKA_Pos)
1583315835
#define GTZC_CFGR3_SDMMC1_Pos (21U)
1583415836
#define GTZC_CFGR3_SDMMC1_Msk (0x01UL << GTZC_CFGR3_SDMMC1_Pos)
1583515837
#define GTZC_CFGR3_FMC_REG_Pos (23U)
@@ -15981,6 +15983,8 @@ typedef struct
1598115983
#define GTZC_TZSC1_SECCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk
1598215984
#define GTZC_TZSC1_SECCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos
1598315985
#define GTZC_TZSC1_SECCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk
15986+
#define GTZC_TZSC1_SECCFGR3_PKA_Pos GTZC_CFGR3_PKA_Pos
15987+
#define GTZC_TZSC1_SECCFGR3_PKA_Msk GTZC_CFGR3_PKA_Msk
1598415988
#define GTZC_TZSC1_SECCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos
1598515989
#define GTZC_TZSC1_SECCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk
1598615990
#define GTZC_TZSC1_SECCFGR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos
@@ -16088,6 +16092,8 @@ typedef struct
1608816092
#define GTZC_TZSC1_PRIVCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk
1608916093
#define GTZC_TZSC1_PRIVCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos
1609016094
#define GTZC_TZSC1_PRIVCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk
16095+
#define GTZC_TZSC1_PRIVCFGR3_PKA_Pos GTZC_CFGR3_PKA_Pos
16096+
#define GTZC_TZSC1_PRIVCFGR3_PKA_Msk GTZC_CFGR3_PKA_Msk
1609116097
#define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos
1609216098
#define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk
1609316099
#define GTZC_TZSC1_PRIVCFGR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos
@@ -16194,6 +16200,8 @@ typedef struct
1619416200
#define GTZC_TZIC1_IER3_HASH_Msk GTZC_CFGR3_HASH_Msk
1619516201
#define GTZC_TZIC1_IER3_RNG_Pos GTZC_CFGR3_RNG_Pos
1619616202
#define GTZC_TZIC1_IER3_RNG_Msk GTZC_CFGR3_RNG_Msk
16203+
#define GTZC_TZIC1_IER3_PKA_Pos GTZC_CFGR3_PKA_Pos
16204+
#define GTZC_TZIC1_IER3_PKA_Msk GTZC_CFGR3_PKA_Msk
1619716205
#define GTZC_TZIC1_IER3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos
1619816206
#define GTZC_TZIC1_IER3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk
1619916207
#define GTZC_TZIC1_IER3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos
@@ -16344,6 +16352,8 @@ typedef struct
1634416352
#define GTZC_TZIC1_SR3_HASH_Msk GTZC_CFGR3_HASH_Msk
1634516353
#define GTZC_TZIC1_SR3_RNG_Pos GTZC_CFGR3_RNG_Pos
1634616354
#define GTZC_TZIC1_SR3_RNG_Msk GTZC_CFGR3_RNG_Msk
16355+
#define GTZC_TZIC1_SR3_PKA_Pos GTZC_CFGR3_PKA_Pos
16356+
#define GTZC_TZIC1_SR3_PKA_Msk GTZC_CFGR3_PKA_Msk
1634716357
#define GTZC_TZIC1_SR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos
1634816358
#define GTZC_TZIC1_SR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk
1634916359
#define GTZC_TZIC1_SR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos
@@ -16494,6 +16504,8 @@ typedef struct
1649416504
#define GTZC_TZIC1_FCR3_HASH_Msk GTZC_CFGR3_HASH_Msk
1649516505
#define GTZC_TZIC1_FCR3_RNG_Pos GTZC_CFGR3_RNG_Pos
1649616506
#define GTZC_TZIC1_FCR3_RNG_Msk GTZC_CFGR3_RNG_Msk
16507+
#define GTZC_TZIC1_FCR3_PKA_Pos GTZC_CFGR3_PKA_Pos
16508+
#define GTZC_TZIC1_FCR3_PKA_Msk GTZC_CFGR3_PKA_Msk
1649716509
#define GTZC_TZIC1_FCR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos
1649816510
#define GTZC_TZIC1_FCR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk
1649916511
#define GTZC_TZIC1_FCR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos
@@ -20161,7 +20173,6 @@ typedef struct
2016120173

2016220174
/******************************* USB DRD FS PCD Instances *************************/
2016320175
#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S))
20164-
2016520176
/** @} */ /* End of group STM32H5xx_Peripheral_Exported_macros */
2016620177

2016720178
/** @} */ /* End of group STM32H523xx */

‎stm32h5xx/Include/stm32h533xx.h

+3-8
Original file line numberDiff line numberDiff line change
@@ -242,11 +242,6 @@ typedef struct
242242
uint32_t RESERVED2; /*!< Reserved, 0x0C */
243243
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
244244
__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
245-
uint32_t RESERVED3[246]; /*!< Reserved, */
246-
__IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */
247-
__IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */
248-
__IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */
249-
__IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */
250245
} CRC_TypeDef;
251246

252247
/**
@@ -3865,7 +3860,7 @@ typedef struct
38653860
#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
38663861
#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
38673862
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
3868-
#define ADC_AWD3CR_AWD2CH_19 (0x80000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00080000 */
3863+
#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
38693864

38703865
/******************** Bit definition for ADC_DIFSEL register ****************/
38713866
#define ADC_DIFSEL_DIFSEL_Pos (0U)
@@ -9163,7 +9158,7 @@ typedef struct
91639158
#define GPIO_HSLVR_HSLV10_Msk (0x1UL << GPIO_HSLVR_HSLV10_Pos) /*!< 0x00000400 */
91649159
#define GPIO_HSLVR_HSLV10 GPIO_HSLVR_HSLV10_Msk
91659160
#define GPIO_HSLVR_HSLV11_Pos (11U)
9166-
#define GPIO_HSLVR_HSLV11_Msk (x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */
9161+
#define GPIO_HSLVR_HSLV11_Msk (0x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */
91679162
#define GPIO_HSLVR_HSLV11 GPIO_HSLVR_HSLV11_Msk
91689163
#define GPIO_HSLVR_HSLV12_Pos (12U)
91699164
#define GPIO_HSLVR_HSLV12_Msk (0x1UL << GPIO_HSLVR_HSLV12_Pos) /*!< 0x00001000 */
@@ -9213,7 +9208,7 @@ typedef struct
92139208
#define GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) /*!< 0x00000400 */
92149209
#define GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk
92159210
#define GPIO_SECCFGR_SEC11_Pos (11U)
9216-
#define GPIO_SECCFGR_SEC11_Msk (x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */
9211+
#define GPIO_SECCFGR_SEC11_Msk (0x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */
92179212
#define GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk
92189213
#define GPIO_SECCFGR_SEC12_Pos (12U)
92199214
#define GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) /*!< 0x00001000 */

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