cli: do not override the ports= parameter of {rtlil,...}.convert().

cli.py

@@ -1,9 +1,58 @@
 import argparse
 from amaranth import cli
+from amaranth.back import rtlil, cxxrtl, verilog
 
 from minerva.core import Minerva
 
 
+__all__ = ["main"]
+
+
+def main_parser(parser=None):
+    if parser is None:
+        parser = argparse.ArgumentParser()
+
+    p_action = parser.add_subparsers(dest="action")
+
+    p_generate = p_action.add_parser("generate",
+            help="generate RTLIL, Verilog or CXXRTL from the design")
+    p_generate.add_argument("-t", "--type",
+            dest="generate_type", metavar="LANGUAGE", choices=["il", "cc", "v"],
+            help="generate LANGUAGE (il for RTLIL, v for Verilog, cc for CXXRTL; "
+                 "default: file extension of FILE, if given)")
+    p_generate.add_argument("--no-src",
+            dest="emit_src", default=True, action="store_false",
+            help="suppress generation of source location attributes")
+    p_generate.add_argument("generate_file",
+            metavar="FILE", type=argparse.FileType("w"), nargs="?",
+            help="write generated code to FILE")
+
+    return parser
+
+
+def main_runner(parser, args, design, name="top"):
+    if args.action == "generate":
+        generate_type = args.generate_type
+        if generate_type is None and args.generate_file:
+            if args.generate_file.name.endswith(".il"):
+                generate_type = "il"
+            if args.generate_file.name.endswith(".cc"):
+                generate_type = "cc"
+            if args.generate_file.name.endswith(".v"):
+                generate_type = "v"
+        if generate_type is None:
+            parser.error("Unable to auto-detect language, specify explicitly with -t/--type")
+        if generate_type == "il":
+            output = rtlil.convert(design, name=name, emit_src=args.emit_src)
+        if generate_type == "cc":
+            output = cxxrtl.convert(design, name=name, emit_src=args.emit_src)
+        if generate_type == "v":
+            output = verilog.convert(design, name=name, emit_src=args.emit_src)
+        if args.generate_file:
+            args.generate_file.write(output)
+        else:
+            print(output)
+
 def main():
     parser = argparse.ArgumentParser(formatter_class=argparse.ArgumentDefaultsHelpFormatter)
 
@@ -61,7 +110,7 @@ def main():
             type=int, default=8,
             help="write buffer depth")
 
-    cli.main_parser(parser)
+    main_parser(parser)
 
     args = parser.parse_args()
 
@@ -74,24 +123,7 @@ def main():
             args.with_muldiv,
             args.with_rvfi)
 
-    ports = [
-        cpu.fast_interrupt, cpu.external_interrupt, cpu.timer_interrupt, cpu.software_interrupt,
-        cpu.ibus.ack, cpu.ibus.adr, cpu.ibus.bte, cpu.ibus.cti, cpu.ibus.cyc, cpu.ibus.dat_r,
-        cpu.ibus.dat_w, cpu.ibus.sel, cpu.ibus.stb, cpu.ibus.we, cpu.ibus.err,
-        cpu.dbus.ack, cpu.dbus.adr, cpu.dbus.bte, cpu.dbus.cti, cpu.dbus.cyc, cpu.dbus.dat_r,
-        cpu.dbus.dat_w, cpu.dbus.sel, cpu.dbus.stb, cpu.dbus.we, cpu.dbus.err
-    ]
-
-    if args.with_rvfi:
-        ports += [
-            cpu.rvfi.valid, cpu.rvfi.order, cpu.rvfi.insn, cpu.rvfi.trap, cpu.rvfi.halt,
-            cpu.rvfi.intr, cpu.rvfi.mode, cpu.rvfi.ixl, cpu.rvfi.rs1_addr, cpu.rvfi.rs2_addr,
-            cpu.rvfi.rs1_rdata, cpu.rvfi.rs2_rdata, cpu.rvfi.rd_addr, cpu.rvfi.rd_wdata,
-            cpu.rvfi.pc_rdata, cpu.rvfi.pc_wdata, cpu.rvfi.mem_addr, cpu.rvfi.mem_rmask,
-            cpu.rvfi.mem_wmask, cpu.rvfi.mem_rdata, cpu.rvfi.mem_wdata,
-        ]
-
-    cli.main_runner(parser, args, cpu, name="minerva_cpu", ports=ports)
+    main_runner(parser, args, cpu, name="minerva_cpu")
 
 
 if __name__ == "__main__":