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Merge remote-tracking branch 'tonioni/master'
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@midwan
midwan committed Jan 11, 2025
2 parents 32eda0b + d26e77d commit df73e16
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Showing 41 changed files with 4,455 additions and 4,287 deletions.
3 changes: 2 additions & 1 deletion blitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -453,7 +453,7 @@ static void blitter_end(void)
static void blitter_done_all(bool all)
{
blt_info.blit_main = 0;
blt_info.blit_queued = BLITTER_MAX_PIPELINED_CYCLES;
blt_info.blit_queued = blitter_cycle_exact ? BLITTER_MAX_PIPELINED_CYCLES : 0;
blt_info.finishcycle_dmacon = get_cycles();
blt_info.finishcycle_copper = get_cycles() + 1 * CYCLE_UNIT;
blitter_interrupt();
Expand Down Expand Up @@ -2034,6 +2034,7 @@ void do_blitter(int copper, uaecptr pc)
blit_totalcyclecounter = 0;
blt_info.blit_pending = 1;
blt_info.blit_count_done = 0;
blt_info.blit_queued = 0;

blitter_start_init();

Expand Down
2 changes: 1 addition & 1 deletion cfgfile.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2478,7 +2478,7 @@ void cfgfile_save_options (struct zfile *f, struct uae_prefs *p, int type)
cfgfile_dwrite_strarr(f, _T("gfx_overscanmode"), overscanmodes, p->gfx_overscanmode);
cfgfile_dwrite(f, _T("gfx_monitorblankdelay"), _T("%d"), p->gfx_monitorblankdelay);
cfgfile_dwrite(f, _T("gfx_rotation"), _T("%d"), p->gfx_rotation);
cfgfile_dwrite (f, _T("gfx_bordercolor"), _T("%08x"), p->gfx_bordercolor);
cfgfile_dwrite (f, _T("gfx_bordercolor"), _T("0x%08x"), p->gfx_bordercolor);

#ifdef GFXFILTER
for (int j = 0; j < MAX_FILTERDATA; j++) {
Expand Down
4 changes: 0 additions & 4 deletions cia.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1027,10 +1027,6 @@ static void resetwarning_check(void)
}
}

void CIA_hsync_prehandler (void)
{
}

void cia_keyreq(uae_u8 code)
{
#if KB_DEBUG
Expand Down
24 changes: 12 additions & 12 deletions cpuemu_0.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -37636,7 +37636,7 @@ uae_u32 REGPARAM2 op_e8c0_0_ff(uae_u32 opcode)
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
Expand Down Expand Up @@ -37831,7 +37831,7 @@ uae_u32 REGPARAM2 op_e9c0_0_ff(uae_u32 opcode)
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
Expand Down Expand Up @@ -38034,14 +38034,14 @@ uae_u32 REGPARAM2 op_eac0_0_ff(uae_u32 opcode)
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = tmp ^ (0xffffffffu >> (32 - width));
tmp = bdata[0] | (tmp << (32 - width));
m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp;
m68k_incpc(4);
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
}
Expand Down Expand Up @@ -38192,7 +38192,7 @@ uae_u32 REGPARAM2 op_ebc0_0_ff(uae_u32 opcode)
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp = (uae_s32)tmp >> (32 - width);
Expand Down Expand Up @@ -38395,14 +38395,14 @@ uae_u32 REGPARAM2 op_ecc0_0_ff(uae_u32 opcode)
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = 0;
tmp = bdata[0] | (tmp << (32 - width));
m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp;
m68k_incpc(4);
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
}
Expand Down Expand Up @@ -38554,7 +38554,7 @@ uae_u32 REGPARAM2 op_edc0_0_ff(uae_u32 opcode)
uae_u32 offset2 = offset;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
Expand Down Expand Up @@ -38780,14 +38780,14 @@ uae_u32 REGPARAM2 op_eec0_0_ff(uae_u32 opcode)
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = 0xffffffffu >> (32 - width);
tmp = bdata[0] | (tmp << (32 - width));
m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp;
m68k_incpc(4);
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
}
Expand Down Expand Up @@ -38938,7 +38938,7 @@ uae_u32 REGPARAM2 op_efc0_0_ff(uae_u32 opcode)
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
Expand All @@ -38948,7 +38948,7 @@ uae_u32 REGPARAM2 op_efc0_0_ff(uae_u32 opcode)
SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0);
SET_ZFLG(tmp == 0);
tmp = bdata[0] | (tmp << (32 - width));
m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp;
m68k_incpc(4);
return (4 * CYCLE_UNIT / 2 + count_cycles) | (((1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4) << 16);
}
Expand Down
24 changes: 12 additions & 12 deletions cpuemu_20.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -39377,7 +39377,7 @@ uae_u32 REGPARAM2 op_e8c0_20_ff(uae_u32 opcode)
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
Expand Down Expand Up @@ -39580,7 +39580,7 @@ uae_u32 REGPARAM2 op_e9c0_20_ff(uae_u32 opcode)
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
Expand Down Expand Up @@ -39791,14 +39791,14 @@ uae_u32 REGPARAM2 op_eac0_20_ff(uae_u32 opcode)
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = tmp ^ (0xffffffffu >> (32 - width));
tmp = bdata[0] | (tmp << (32 - width));
m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp;
regs.irc = get_word_020_prefetch(4);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
Expand Down Expand Up @@ -39955,7 +39955,7 @@ uae_u32 REGPARAM2 op_ebc0_20_ff(uae_u32 opcode)
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp = (uae_s32)tmp >> (32 - width);
Expand Down Expand Up @@ -40166,14 +40166,14 @@ uae_u32 REGPARAM2 op_ecc0_20_ff(uae_u32 opcode)
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = 0;
tmp = bdata[0] | (tmp << (32 - width));
m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp;
regs.irc = get_word_020_prefetch(4);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
Expand Down Expand Up @@ -40331,7 +40331,7 @@ uae_u32 REGPARAM2 op_edc0_20_ff(uae_u32 opcode)
uae_u32 offset2 = offset;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
Expand Down Expand Up @@ -40565,14 +40565,14 @@ uae_u32 REGPARAM2 op_eec0_20_ff(uae_u32 opcode)
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = 0xffffffffu >> (32 - width);
tmp = bdata[0] | (tmp << (32 - width));
m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp;
regs.irc = get_word_020_prefetch(4);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
Expand Down Expand Up @@ -40729,7 +40729,7 @@ uae_u32 REGPARAM2 op_efc0_20_ff(uae_u32 opcode)
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
Expand All @@ -40739,7 +40739,7 @@ uae_u32 REGPARAM2 op_efc0_20_ff(uae_u32 opcode)
SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0);
SET_ZFLG(tmp == 0);
tmp = bdata[0] | (tmp << (32 - width));
m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp;
regs.irc = get_word_020_prefetch(4);
m68k_incpci(4);
return (1 * 4 * CYCLE_UNIT / 2 + count_cycles) * 4;
Expand Down
24 changes: 12 additions & 12 deletions cpuemu_21.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -42622,7 +42622,7 @@ void REGPARAM2 op_e8c0_21_ff(uae_u32 opcode)
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
Expand Down Expand Up @@ -42841,7 +42841,7 @@ void REGPARAM2 op_e9c0_21_ff(uae_u32 opcode)
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
Expand Down Expand Up @@ -43068,14 +43068,14 @@ void REGPARAM2 op_eac0_21_ff(uae_u32 opcode)
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = tmp ^ (0xffffffffu >> (32 - width));
tmp = bdata[0] | (tmp << (32 - width));
m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp;
regs.irc = get_word_ce020_prefetch_opcode(4);
m68k_incpci(4);
return;
Expand Down Expand Up @@ -43244,7 +43244,7 @@ void REGPARAM2 op_ebc0_21_ff(uae_u32 opcode)
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp = (uae_s32)tmp >> (32 - width);
Expand Down Expand Up @@ -43471,14 +43471,14 @@ void REGPARAM2 op_ecc0_21_ff(uae_u32 opcode)
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = 0;
tmp = bdata[0] | (tmp << (32 - width));
m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp;
regs.irc = get_word_ce020_prefetch_opcode(4);
m68k_incpci(4);
return;
Expand Down Expand Up @@ -43648,7 +43648,7 @@ void REGPARAM2 op_edc0_21_ff(uae_u32 opcode)
uae_u32 offset2 = offset;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
Expand Down Expand Up @@ -43898,14 +43898,14 @@ void REGPARAM2 op_eec0_21_ff(uae_u32 opcode)
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
SET_ZFLG(tmp == 0); SET_VFLG(0); SET_CFLG(0);
tmp = 0xffffffffu >> (32 - width);
tmp = bdata[0] | (tmp << (32 - width));
m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp;
regs.irc = get_word_ce020_prefetch_opcode(4);
m68k_incpci(4);
return;
Expand Down Expand Up @@ -44074,7 +44074,7 @@ void REGPARAM2 op_efc0_21_ff(uae_u32 opcode)
int width = (((extra & 0x20 ? m68k_dreg(regs, extra & 7) : extra) - 1) & 0x1f) + 1;
uae_u32 tmp = m68k_dreg(regs, dstreg);
offset &= 0x1f;
tmp = (tmp << offset) | (tmp >> (32 - offset));
if (offset) tmp = (tmp << offset) | (tmp >> (32 - offset));
bdata[0] = tmp & ((1 << (32 - width)) - 1);
SET_ALWAYS_NFLG(((uae_s32)tmp) < 0 ? 1 : 0);
tmp >>= (32 - width);
Expand All @@ -44084,7 +44084,7 @@ void REGPARAM2 op_efc0_21_ff(uae_u32 opcode)
SET_ALWAYS_NFLG(tmp & (1 << (width - 1)) ? 1 : 0);
SET_ZFLG(tmp == 0);
tmp = bdata[0] | (tmp << (32 - width));
m68k_dreg(regs, dstreg) = (tmp >> offset) | (tmp << (32 - offset));
m68k_dreg(regs, dstreg) = offset ? ((tmp >> offset) | (tmp << (32 - offset))) : tmp;
regs.irc = get_word_ce020_prefetch_opcode(4);
m68k_incpci(4);
return;
Expand Down
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