Remove redundant memory ordering overrides now that /volatile:ms is used#27
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macarte merged 1 commit intomacarte/rebased-additional-fixesfrom Mar 12, 2026
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With /volatile:ms set in JVM_CFLAGS for Windows AArch64, MSVC gives volatile accesses acquire/release semantics (LDAR/STLR), making several defense-in-depth changes unnecessary and harmful to performance: - Revert orderAccess_windows_aarch64.hpp from __dmb() intrinsics back to std::atomic_thread_fence(). With /volatile:ms, volatile accesses are already compiler-barriered, so std::atomic_thread_fence() works correctly for both compiler and hardware ordering. - Remove PlatformLoad<N> and PlatformStore<N> overrides from atomic_windows_aarch64.hpp. These forced LDAR/STLR on every Atomic::load()/Atomic::store() call, but /volatile:ms already produces identical codegen for the generic volatile-dereference path. The PlatformOrderedLoad/PlatformOrderedStore specializations (for Atomic::load_acquire/release_store) are retained as they provide single-instruction LDAR/STLR instead of the generic dmb+LDR/STR fallback.
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With /volatile:ms set in JVM_CFLAGS for Windows AArch64, MSVC gives volatile accesses acquire/release semantics (LDAR/STLR), making several defense-in-depth changes unnecessary and harmful to performance:
Revert orderAccess_windows_aarch64.hpp from __dmb() intrinsics back to std::atomic_thread_fence(). With /volatile:ms, volatile accesses are already compiler-barriered, so std::atomic_thread_fence() works correctly for both compiler and hardware ordering.
Remove PlatformLoad and PlatformStore overrides from atomic_windows_aarch64.hpp. These forced LDAR/STLR on every Atomic::load()/Atomic::store() call, but /volatile:ms already produces identical codegen for the generic volatile-dereference path. The PlatformOrderedLoad/PlatformOrderedStore specializations (for Atomic::load_acquire/release_store) are retained as they provide single-instruction LDAR/STLR instead of the generic dmb+LDR/STR fallback.