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1. Booth_multiplier Booth_multiplier Public

   Designed a signed 8-bit sequential multiplier using Booth’s algorithm in Verilog. The system uses a state machine and arithmetic right shifts to compute a 16-bit signed product over 8 cycles. Inclu…

   Verilog

2. master_i2c master_i2c Public

   Verilog

3. smartware smartware Public

   C++

4. mybytes_hdlbits mybytes_hdlbits Public

   Welcome to mybytes_hdlbits! This repository contains my solutions to the Verilog problems from HDLBits. My goal is to share clear, Verilog code to help others learn HDL concepts and improve their s…

   2

5. AMBA_AHB AMBA_AHB Public

   This AMBA AHB project is designed using FSM-based state machines in Verilog, modeled and tested in Vivado with simulation and synthesis tools. The FSM controls master–slave transactions, arbitratio…

   Verilog

6. RISC-V-Single-Cycle-Core RISC-V-Single-Cycle-Core Public

   Verilog