Add Cortex-R support by m-braunschweig · Pull Request #2261 · mcu-tools/mcuboot

m-braunschweig · 2025-04-10T13:23:12Z

This PR adds support for Booting on a Cortex-R core. It has been tested with the following branch which also includes some instructions what Kconfig options need to be set: https://github.com/siemens/zephyr/tree/mika/ti/ti-am2434-native-boot

nordicjm · 2025-04-10T13:31:12Z

+	uint8_t i;
+	uint8_t num_regions;
+	uint32_t mpu_type_register;
+
+	// disable MPU
+	__asm__(
+		"	mrc p15, 0, r0, c1, c0, 0\n"
+		"	bic r0, #1\n"
+		"	mcr p15, 0, r0, c1, c0, 0\n"
+		"	isb\n"
+		::: "r0");
+
+	// the number of MPU regions is stored in bits 15:8 of the MPU type register
+	__asm__ volatile("mrc p15, 0, %0, c0, c0, 4\n" : "=r" (mpu_type_register) ::);
+	num_regions = (uint8_t) ((mpu_type_register >> 8) & BIT_MASK(8));
+
+	for (i = 0; i < num_regions; ++i) {
+		// select region in the MPU and clear the region size field
+		__asm__ volatile(
+			"	mov r0, #0\n"
+			"	mcr p15, 0, %0, c6, c2, 0\n"
+			"	mcr p15, 0, r0, c6, c1, 2\n"
+			:: "r" (i) : "r0");
+	}


should be using zephyr APIs, should not be adding code, let alone assembly, here to do this (applies to clearing MPU, the boot assembly code is fine)

I agree that the inline assmebly isn't really good here. I was also thinking about using Zephyr functions but then noticed that arm_core_mpu_disable is not public (as in: Not in any header) and only interally used, meaning it could change.

For disabling (clearing) the individual regions Zephyr has a non-public header that provides ARM_MPU_ClrRegion (link), which is the same name CMSIS provides only for Cortex-M cores.

nordicjm · 2025-04-10T13:31:42Z


 /*
 * Copyright (c) 2020 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Siemens Mobility GmbH


m-braunschweig · 2025-04-10T15:11:59Z

Thanks for the review. I addressed the changes in the last force-push and added a comment to the MPU

m-braunschweig · 2025-06-13T13:56:00Z

@nordicjm can you please take a look again? I changed the MPU code to be more readable via macros but if you insist I can also add a #include <zephyr/../../arch/arm/core/mpu/cortex_a_r/arm_mpu_internal.h> to use the internal Zephyr functions.

Also sorry but I didn't notice that I removed the Copyright notices for the small changes in the release note commit instead of the original commit while rebasing

nordicjm

Is OK to add, just needs nit. fixes

nordicjm · 2025-06-16T06:11:03Z

+
+#endif /* CONFIG_CPU_CORTEX_R5 */
+
+void cleanup_arm_interrupts(void) {


newline for {

nordicjm · 2025-06-16T06:11:24Z

 		NVIC->ICPR[i] = 0xFFFFFFFF;
 	}
+#else
+


Suggested change

m-braunschweig · 2025-06-16T07:08:56Z

First force-push is a capitalize first letter in the comment fix that I previously missed; second force-push are your suggestions.

Do you mean it's ok to add the internal header or the inline ASM to read/write coprocessor registers via the macros?

nordicjm · 2025-06-16T07:47:08Z

First force-push is a capitalize first letter in the comment fix that I previously missed; second force-push are your suggestions.

Do you mean it's ok to add the internal header or the inline ASM to read/write coprocessor registers via the macros?

PR is OK as-is, would be good to move from here to zephyr itself then just call from here but that is optional/nice to have not required

nordicjm · 2025-06-18T08:50:47Z

@m-braunschweig seemingly this branch has conflicts that must be resolved? Not sure what those are but can you check and fix?

nvlsianpu

Can we have explicate ifdefry
#ifdef CONFIG_CPU_CORTEX_R5
for code for supporting Cortex-R in that patch.
This would help wit maintenance and improve legibility of Cortex-R relevant code.

nvlsianpu · 2025-06-18T11:33:16Z

 #endif

-void cleanup_arm_nvic(void) {
+#ifndef CONFIG_CPU_CORTEX_M


is this only for CONFIG_CPU_CORTEX_R5?

Currently yes. The GIC is also ARM specific while z_soc_irq_eoi should is architecture agnostic

m-braunschweig · 2025-06-23T12:38:34Z

@m-braunschweig seemingly this branch has conflicts that must be resolved? Not sure what those are but can you check and fix?

Resolved. Was due to the Copyright line in the main.c

Can we have explicate ifdefry #ifdef CONFIG_CPU_CORTEX_R5 for code for supporting Cortex-R in that patch. This would help wit maintenance and improve legibility of Cortex-R relevant code.

Yeah. Are you fine with me splitting the arm_cleanup.c into cleanup/arm_cortex_m.c and cleanup/arm_cortex_r.c with both providing the same functions and only one being compiled via CMake? For the main.c I don't have an idea currently on how to effectivly remove/decrease the #ifdefs

nvlsianpu · 2025-06-25T14:12:11Z

@m-braunschweig I actually men rather using #ifdef CONFIG_CPU_CORTEX_R for code dedicated for Cortex-R than #ifndef CONFIG_CPU_CORTEX_M. If you want to go with separate files/functions - that will help wit clean code as well.

m-braunschweig · 2025-07-04T08:56:38Z

Updated it. One problem is that we can't use CONFIG_CPU_CORTEX_R since that Kconfig option doesn't exist in Zephyr. For now I only use CONFIG_CPU_CORTEX_R5 since that's the exact core I'm using to test the code.

Edit: I just saw CONFIG_ARMV7_R exists. I will update it now

Add Cortex-R support by using ifdefs to change the vector table, remove CORTEX_M only code and do an explicit bx instruction to switch from Thumb to ARM mode on exit of the MCUboot application. Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>

Add code to cleanup the Cortex-R processor state to the reset configuration and disable + acknowledge all interrupts before entering the booted application. Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>

Add notes about the additions made in order to support Cortex-R booting. Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>

m-braunschweig · 2025-07-04T09:08:11Z

Updated it to use ARMV7_R and also the comment for Cortex-R to be more accurate

natto1784 · 2025-07-09T07:51:00Z

+#ifdef CONFIG_CPU_CORTEX_M
    __set_CONTROL(0x00); /* application will configures core on its own */
    __ISB();
+#else


I am good with it as it is but can we do #ifdef CONFIG_ARMV7_R here just to make the use case clearer. Same with other #elses as well?

can be improved in this PR or in a next one.

natto1784

Great addition, aside from my other comment, this looks good enough as it is

nvlsianpu · 2025-07-17T07:36:37Z

+#ifdef CONFIG_CPU_CORTEX_M
    __set_CONTROL(0x00); /* application will configures core on its own */
    __ISB();
+#else


can be improved in this PR or in a next one.

m-braunschweig · 2025-07-18T14:34:29Z

I will try to remember to do the changes when submitting a PR that provides default configs for the AM243x LaunchPad (which isn't supported by upstream Zephyr yet)

m-braunschweig requested review from d3zd3z, de-nordic and nordicjm as code owners April 10, 2025 13:23

nordicjm requested changes Apr 10, 2025

View reviewed changes

m-braunschweig force-pushed the mika/upstream/add-cortex-r-support branch from 604b494 to d4a3922 Compare April 10, 2025 14:56

m-braunschweig requested a review from nordicjm April 10, 2025 15:12

m-braunschweig force-pushed the mika/upstream/add-cortex-r-support branch 2 times, most recently from 72d9beb to 783871b Compare June 13, 2025 13:54

nordicjm reviewed Jun 16, 2025

View reviewed changes

m-braunschweig force-pushed the mika/upstream/add-cortex-r-support branch 2 times, most recently from 4ed8635 to 5b4dfa2 Compare June 16, 2025 07:07

m-braunschweig requested a review from nordicjm June 16, 2025 07:09

nordicjm approved these changes Jun 16, 2025

View reviewed changes

nordicjm requested a review from nvlsianpu June 18, 2025 06:43

nvlsianpu requested changes Jun 18, 2025

View reviewed changes

nvlsianpu added the area: zephyr Affects the Zephyr port label Jun 18, 2025

m-braunschweig force-pushed the mika/upstream/add-cortex-r-support branch from 5b4dfa2 to 25b2643 Compare June 23, 2025 12:38

m-braunschweig force-pushed the mika/upstream/add-cortex-r-support branch from 25b2643 to 8bf4803 Compare July 4, 2025 08:55

m-braunschweig added 3 commits July 4, 2025 11:04

boot: zephyr: Add support for Cortex-R cleanup before final jump

be93d43

Add code to cleanup the Cortex-R processor state to the reset configuration and disable + acknowledge all interrupts before entering the booted application. Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>

docs: release-notes: Add changes for Cortex-R booting

a3cca64

Add notes about the additions made in order to support Cortex-R booting. Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>

m-braunschweig force-pushed the mika/upstream/add-cortex-r-support branch from 8bf4803 to a3cca64 Compare July 4, 2025 09:07

nordicjm requested a review from nvlsianpu July 8, 2025 15:42

natto1784 reviewed Jul 9, 2025

View reviewed changes

natto1784 approved these changes Jul 9, 2025

View reviewed changes

nvlsianpu approved these changes Jul 17, 2025

View reviewed changes

nvlsianpu merged commit f67df43 into mcu-tools:main Jul 17, 2025
58 checks passed


		#endif /* CONFIG_CPU_CORTEX_R5 */

		void cleanup_arm_interrupts(void) {

Conversation

m-braunschweig commented Apr 10, 2025

Uh oh!

Uh oh!

nordicjm Apr 10, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Uh oh!

Uh oh!

Uh oh!

m-braunschweig commented Apr 10, 2025

Uh oh!

m-braunschweig commented Jun 13, 2025

Uh oh!

nordicjm left a comment

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

m-braunschweig commented Jun 16, 2025

Uh oh!

nordicjm commented Jun 16, 2025

Uh oh!

nordicjm commented Jun 18, 2025

Uh oh!

nvlsianpu left a comment

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

m-braunschweig commented Jun 23, 2025

Uh oh!

nvlsianpu commented Jun 25, 2025

Uh oh!

m-braunschweig commented Jul 4, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

m-braunschweig commented Jul 4, 2025

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

natto1784 left a comment • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Uh oh!

m-braunschweig commented Jul 18, 2025

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

4 participants

nordicjm Apr 10, 2025 •

edited

Loading

m-braunschweig commented Jul 4, 2025 •

edited

Loading

natto1784 left a comment •

edited

Loading