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Interfaces
The FEB has a direct connection with 4 subsystems: Cold Electronics, DAQ, Slow control, and the cryostat interface.
The cables between DAPHNE and the cryostat interface are twisted paired cables supporting 4 analog channels each, for a total of 10 twisted paired cables for one FEB. As the cables were considered for the simplicity of the layout implementation, and the characteristics in terms of the signal stability.
The Slow Control Connection consists of a Fast Ethernet Connection driven by the ST microcontroller, by using 2 external devices: 1 Wiznet module and 1 PHY with optical fiber support. The output of the link is an SFP transceiver, allowing optical fiber, RJ45, and a TCP/IP support. This interface should Handle flags in the power requirements of the Board, temperature monitoring using the XADCs on the FPGA and the General Error Handling of the FEB and Cold Electronics. The FEB implements a server where a register matrix is refreshed in the microcontroller and in the FPGA.
There is a set of debugging pins to perform an event check in case of differences between the simulation and the hardware results.
Daphne counts on two SFP transceivers for data streaming. These are driven directly by the GTP transceivers in FPGA and are 4.8Gb/s capable in streaming mode. At DUNE final assembly only one of these will be used for data streaming. The use of two digital streaming enables us to perform loop corrections at the development level, and at the calibration rounds.
DAQ should provide a system clock of 62.5MHz for triggering and should be connected at the CDR port.
Nevertheless, DAPHNE is prepared to work with an external clock input source at the LEMO connection. This connection will be used during the tests in the absence of a system triggering clock, or with different rates at the streaming output like ICEBERG.
The LEMO output allows us to sync other modules sharing the clock of the FPGA. It could be the LEMO input clock or one of the inner programmable clocks on the FPGA. A control loop can be run to check the clock integrity of some modules or signals.