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SUServo: Coherent phase tracking mode #1467

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SUServo: Coherent phase tracking mode #1467

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2502459
Apply experimental suservo-var-urukul
pmldrmota Sep 10, 2022
bd849c4
Urukul CPLD half-duplex readback support in SUServo configuration.
pmldrmota Sep 10, 2022
fc64ad8
SUServo: Convert io_update to SERDES and connect sync_in to ClockGen.
pmldrmota Sep 10, 2022
e643e47
SUServo: pipelined coherent phase tracking mode.
pmldrmota Sep 12, 2022
9f34725
fixup artiq_ddb_template for SU Servo
pmldrmota Sep 12, 2022
2aff060
coredevice.suservo: clean up IO update alignment measurement
pmldrmota Sep 12, 2022
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12 changes: 10 additions & 2 deletions artiq/coredevice/ad9910.py
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Original file line number Diff line number Diff line change
Expand Up @@ -277,6 +277,10 @@ def read32(self, addr: TInt32) -> TInt32:

:param addr: Register address
"""
return self.read32_impl(addr)

@kernel
def read32_impl(self, addr):
self.bus.set_config_mu(urukul.SPI_CONFIG, 8,
urukul.SPIT_DDS_WR, self.chip_select)
self.bus.write((addr | 0x80) << 24)
Expand Down Expand Up @@ -981,7 +985,8 @@ def clear_smp_err(self):

@kernel
def tune_sync_delay(self,
search_seed: TInt32 = 15) -> TTuple([TInt32, TInt32]):
search_seed: TInt32 = 15,
cpld_channel_idx: TInt32 = -1) -> TTuple([TInt32, TInt32]):
"""Find a stable SYNC_IN delay.

This method first locates a valid SYNC_IN delay at zero validation
Expand All @@ -997,6 +1002,9 @@ def tune_sync_delay(self,
Defaults to 15 (half range).
:return: Tuple of optimal delay and window size.
"""
if cpld_channel_idx == -1:
cpld_channel_idx = self.chip_select - 4
assert 0 <= cpld_channel_idx < 4, "Invalid channel index"
if not self.cpld.sync_div:
raise ValueError("parent cpld does not drive SYNC")
search_span = 31
Expand All @@ -1019,7 +1027,7 @@ def tune_sync_delay(self,
delay(100 * us)
err = urukul_sta_smp_err(self.cpld.sta_read())
delay(100 * us) # slack
if not (err >> (self.chip_select - 4)) & 1:
if not (err >> cpld_channel_idx) & 1:
next_seed = in_delay
break
if next_seed >= 0: # valid delay found, scan next window
Expand Down
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