[ExportVerilog] Move declarations to the top of blocks when disallowDeclAssignments is set. #9309
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…eclAssignments is set. This patch implements the logic to move wire and register declarations to the beginning of blocks when the disallowDeclAssignments option is enabled. This is solely for readability not for correctness.
fabianschuiki
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Dec 10, 2025
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fabianschuiki
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fabianschuiki
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LGTM! Nice to have these bundled up at the top!
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This patch implements the logic to move wire declarations to the beginning of blocks when the disallowDeclAssignments option is enabled. This is solely for readability not for correctness.