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alpha_speedup.py

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+# Utility for RPi Alpha to increase remote GDB baud rate
+# From iosoft.blog, copyright (c) Jeremy P bentham 2020
+# Requires pyserial package
+
+import sys, serial, time
+
+# Defaults
+serport  = "COM7"
+verbose  = False
+
+# Default settings
+OLD_BAUD    = 115200
+new_baud    = 921600
+TIMEOUT     = 0.2
+SYS_CLOCK   = 250e6
+
+# GDB remote commands
+high_speed  = "mw32 0x20215068 %u"
+qsupported  = "qSupported"
+
+# Send command, return response
+def cmd_resp(ser, cmd):
+    txd = frame(cmd)
+    if verbose:
+        print("Tx: %s" % txd)
+    ser.write(txd.encode('latin'))
+    rxd = str(ser.read(1468))
+    if verbose:
+        print("Rx: %s" % rxd)
+    resp = rxd.partition('$')
+    return resp[2].partition('#')[0]
+
+# Acknowledge a response
+def ack_resp(ser):
+    ser.write('+'.encode('latin'))
+    if verbose:
+        print("Tx: +")
+
+# Return string, given hex values
+def hex_str(hex):
+    return bytearray.fromhex(hex).decode()
+
+# Return remote hex command string
+def cmd_hex(cmd):
+    return "qRcmd,%s" % "".join([("%02x" % ord(c)) for c in cmd])
+
+# Return framed data
+def frame(data):
+    return "$%s#%02x" % ("".join([escape(c) for c in data]), csum(data))
+
+# Escape a character in the message
+def escape(c):
+    return c if c not in "#$}" else '}'+chr(ord(c)^0x20)
+
+# GDB checksum calculation
+def csum(data):
+    return 0xff & sum([ord(c) for c in data])
+
+# Open serial port
+def ser_open(port, baud):
+    try:
+        ser = serial.Serial(port, baud, timeout=TIMEOUT)
+    except:
+        print("Can't open serial port %s" % port)
+        sys.exit(1)
+    return ser
+
+# Close serial port
+def ser_close(ser):
+    if ser:
+        ser.close()
+
+if __name__ == "__main__":
+    opt = None
+    for arg in sys.argv[1:]:
+        if len(arg)==2 and arg[0]=="-":
+            opt = arg.lower()
+            if opt == "-v":
+                verbose = True
+                opt = None
+        elif opt == '-b':
+            new_baud = int(arg)
+            opt = None
+        elif opt == '-c':
+            serport = arg
+            opt = None
+    print("Opening serial port %s at %u baud" % (serport, OLD_BAUD))
+    ser = ser_open(serport, OLD_BAUD);
+    cmd_resp(ser, "")
+    ack_resp(ser)
+    if cmd_resp(ser, qsupported):
+        ack_resp(ser)
+        print("Setting %u baud" % new_baud)
+        uart_div = int(round((SYS_CLOCK / (8 * new_baud)) - 1))
+        cmd_resp(ser, cmd_hex(high_speed % uart_div))
+    time.sleep(0.01)
+    print("Reopening at %u baud" % new_baud)
+    ser_close(ser)
+    ser = ser_open(serport, new_baud);
+    ack_resp(ser)
+    if cmd_resp(ser, qsupported):
+        ack_resp(ser)
+        print("Target system responding OK")
+        time.sleep(0.01)
+    else:
+        print("No response from target system")
+#EOF

build_part4

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+arm-none-eabi-gcc -specs=./sdk/Alpha.specs -mfloat-abi=hard -mfpu=vfp -march=armv6zk -mtune=arm1176jzf-s -g3 -ggdb -Wall -Wl,-T./sdk/link.ld -L./sdk -Wl,-umalloc -fpack-struct=1 -o zerowi.elf srce/part4.c srce/zw_sdio.c srce/zw_ioctl.c srce/zw_gpio.c

build_part4.bat

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+arm-none-eabi-gcc -specs=./sdk/Alpha.specs -mfloat-abi=hard -mfpu=vfp -march=armv6zk -mtune=arm1176jzf-s -g3 -ggdb -Wall -Wl,-T./sdk/link.ld -L./sdk -Wl,-umalloc -fpack-struct=1 -o zerowi.elf srce/part4.c srce/zw_sdio.c srce/zw_ioctl.c srce/zw_gpio.c

run

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+python alpha_speedup.py -c /dev/ttyUSB0 -b 460800
+arm-none-eabi-gdb -x run_lin.gdb zerowi.elf

run.bat

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+python alpha_speedup.py -c com7
+arm-none-eabi-gdb -x run_win.gdb zerowi.elf

run_lin.gdb

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+# Connect GDB serial to RPi: pin 5 black, 7 yellow, 9 red
+source sdk/alpha.gdb
+
+#set serial baud 921600
+#target remote COM7
+
+set serial baud 460800
+target remote /dev/ttyUSB0
+
+# Load the executable in the target
+# By default, the loaded file is the one GDB debugs, given as argument
+# to gdb or using the command file.
+load
+
+# Run untile reaching main
+# tbreak main
+break gdb_break
+commands 1
+  kill
+  quit
+end
+continue

run_win.gdb

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+# Connect GDB serial to RPi: pin 5 black, 7 yellow, 9 red
+source sdk/alpha.gdb
+
+set serial baud 921600
+target remote COM7
+#target remote /dev/ttyUSB0
+
+# Load the executable in the target
+# By default, the loaded file is the one GDB debugs, given as argument
+# to gdb or using the command file.
+load
+
+# Run untile reaching main
+# tbreak main
+break gdb_break
+commands 1
+  kill
+  quit
+end
+continue

sdk/Alpha.specs

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+%rename link_gcc_c_sequence nosys_link_gcc_c_sequence
+
+*Alpha_libgloss:
+-lfileio -lalpha -larm
+
+*nosys_libc:
+%{!specs=nano.specs:-lc} %{specs=nano.specs:-lc_nano}
+
+*link_gcc_c_sequence:
+%(nosys_link_gcc_c_sequence) --start-group %G  %(nosys_libc)  %(Alpha_libgloss)  --end-group

sdk/CPU_init.c

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+
+
+/* This function initialise the MMU with the following mapping */
+/*        Physical 0x00000000 - 0x20000000, virtual 0x00000000 - 0x20000000,   RWX user, RWX super, write-back, no write allocate */
+/* RPI1   Physical 0x20000000 - 0x21000000, virtual 0x20000000 - 0x21000000,   RWX user, RWX super, write-back, no-cacheable */
+/* RPI2&3 Physical 0x3F000000 - 0x40000000, virtual 0x20000000 - 0x21000000,   RWX user, RWX super, write-back, no-cacheable */
+/*        Physical 0x00000000 - 0x40000000, virtual 0x40000000 - 0x80000000,   RWX user, RWX super, write-back, no-cacheable */
+
+/* The CPU RAM size is limited to 512 to fit almost all raspberry */
+/* The Whole RAM is accessible in non-cacheable mode from 0x40000000 to be able to access video RAM */
+
+
+#define RPI1_IO_BASE_ADDRESS       0x20000000
+#define RPI2_IO_BASE_ADDRESS       0x3F000000
+#define RPI3_IO_BASE_ADDRESS       0x3F000000
+
+
+/* number of 1M section in 4 GB address space */
+#define NB_1M_SECTION (0x100000000LL / 0x00100000)
+extern unsigned int CPU_init_page_table[NB_1M_SECTION];
+
+/* */
+#define ONE_MB  (1024 * 1024)
+#define K_RAM_SIZE (512 *K_1M)
+
+extern unsigned int CPU_init_read_main_id();
+extern void CPU_init_stop_mmu();
+extern void CPU_init_start_mmu(unsigned int * page_table,unsigned int control_register_or_mask);
+extern void CPU_init_enable_vfp();
+extern void CPU_init_invalidate_tlb();
+extern void CPU_init_clean_and_invalidate_data_cache();
+extern void CPU_init_invalidate_instruction_cache();
+extern void CPU_init_disable_caches();
+
+void CPU_init_map_section(
+   unsigned int  *page_table,
+   unsigned int   virtual_address,
+   unsigned int   physical_address,
+   unsigned int   flags)
+{
+   unsigned int   *entry;
+
+   entry = &(page_table[virtual_address >> 20]);
+   *entry = (physical_address & 0xFFF00000) | flags | 2 |0xC00;
+   return;
+}
+
+
+
+void CPU_init()
+{
+   unsigned int main_id;
+   unsigned int physical_io_address;
+   unsigned int i;
+
+   /* reading CPU id to known RPI version */
+   main_id = CPU_init_read_main_id();
+
+   /* rpi1 armv6 */
+   if ((main_id & 0xF000) == 0xB000)
+   {
+      physical_io_address = RPI1_IO_BASE_ADDRESS;
+   }
+   /* rpi2 armv7 */
+   else if ((main_id & 0xF000) == 0xC000)
+   {
+      physical_io_address = RPI2_IO_BASE_ADDRESS;
+   }
+   /* rpi3 armv8 */
+   else if ((main_id & 0xF000) == 0xD000)
+   {
+      physical_io_address = RPI3_IO_BASE_ADDRESS;
+   }
+
+   /* clear page table */
+   for (i = 0;i < NB_1M_SECTION; i++)
+   {
+      CPU_init_page_table[i] = 0;
+   }
+
+   /* map     Physical 0x00000000 - 0x20000000, virtual 0x00000000 - 0x20000000,   RWX user, RWX super, write-back, no write allocate */
+   for (i = 0x00000000; i < (512 * ONE_MB); i+= ONE_MB)
+   {
+      CPU_init_map_section(CPU_init_page_table,i,i,0x0c); // cacheable no write allocate
+   }
+
+   /* RPI1   Physical 0x20000000 - 0x21000000, virtual 0x20000000 - 0x21000000,   RWX user, RWX super, write-back, no-cacheable */
+   /* RPI2&3 Physical 0x3F000000 - 0x40000000, virtual 0x20000000 - 0x21000000,   RWX user, RWX super, write-back, no-cacheable */
+   for (i = 0; i < (16 * ONE_MB) ; i+= ONE_MB)
+   {
+      CPU_init_map_section(CPU_init_page_table,RPI1_IO_BASE_ADDRESS + i,physical_io_address + i,0); // not cacheable
+   }
+
+   /* Map    Physical 0x00000000 - 0x40000000, virtual 0x40000000 - 0x80000000,   RWX user, RWX super, write-back, no-cacheable */
+   for (i = 0x00000000; i < 0x40000000; i+= ONE_MB)
+   {
+      CPU_init_map_section(CPU_init_page_table,0x40000000 + i,i,0x0); // not cacheable
+   }
+
+//   clean_and_invalidate_data_cache();
+//   invalidate_instruction_cache();
+//   disable_caches();
+   CPU_init_stop_mmu();
+   CPU_init_invalidate_tlb();
+   CPU_init_start_mmu((unsigned int *)((unsigned int)CPU_init_page_table),0x1005); /* ICACHE DCACHE and MMU ON */
+   CPU_init_enable_vfp();
+
+   return;
+}

sdk/CPU_init_util.S

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+        .text
+
+        .globl CPU_init_stop_mmu
+        .globl CPU_init_start_mmu
+        .globl CPU_init_enable_vfp
+        .globl CPU_init_invalidate_tlb
+        .globl CPU_init_clean_and_invalidate_data_cache
+        .globl CPU_init_invalidate_instruction_cache
+        .globl CPU_init_disable_caches
+        .globl CPU_init_read_main_id
+
+
+CPU_init_read_main_id:
+        MRC    p15,0,r0,c0,c0,0
+        BX     lr    
+
+
+CPU_init_clean_and_invalidate_data_cache:
+        // flush data cache
+loop:   
+        MOV         r2,#0
+        MCR         p15,0,r2,c7,c10,0
+        MRC         p15,0,r2,c7,c10,6
+        ANDS        r2,r2,#01
+        BEQ         done
+        B           loop
+done:
+        // invalidate data cache */
+        MCR         p15,0,r2,c7,c6,0
+        MCR         p15,0,r2,c7,c10,4
+        BX          lr
+
+
+
+CPU_init_invalidate_instruction_cache:    
+        MOV         r2,#0
+        MCR         p15,0,r2,c7,c5,0
+        MCR         p15,0,r2,c7,c10,4
+        BX          lr
+
+
+CPU_init_disable_caches:  
+        MRC         p15,0,r2,c1,c0,0
+        BIC         r2,#0x1000
+        BIC         r2,#0x0004
+        MCR         p15,0,r2,c1,c0,0
+        BX          lr
+
+
+CPU_init_stop_mmu:
+        // disable mmu 
+        MRC    p15,0,r2,c1,c0,0
+        BIC    r2,#0x01
+        MCR    p15,0,r2,c1,c0,0
+        BX     lr
+
+CPU_init_start_mmu:
+//set domain register to 0x55555555 to allow client access  to perform check        
+        LDR    r2,=0x55555555
+        MCR    p15,0,r2,c3,c0,0 ;@ domain
+// clear TTBC to enable only TTBR0
+        MOV    r2,#0    
+        MCR    p15,0,r2,c2,c0,2 ;@ TTBC
+// set TTBR0 to pagetable address
+        MRC    p15,0,r4,c2,c0,0 ;@ tlb base
+        MCR    p15,0,r0,c2,c0,0 ;@ tlb base
+        MCR    p15,0,r0,c2,c0,1 ;@ tlb base
+        MOV    r2,#0
+        MCR    p15,0,r2,c7,c10,4
+
+        // write in control register input value
+        MRC    p15,0,r2,c1,c0,0
+        ORR    r2,r2,r1
+        MCR    p15,0,r2,c1,c0,0
+        BX     lr
+
+
+        /* enable copro single doucle precision */
+        /* enable float */
+        /* set fpscr to flush to zero */
+CPU_init_enable_vfp:
+        //@ en@ enable the FPU
+        MRC     p15, 0, r0, c1, c0, 2
+        ORR     r0, r0, #0x300000            /* single precision */
+        ORR     r0, r0, #0xC00000            /* double precision */
+        MCR     p15, 0, r0, c1, c0, 2
+        MOV     r0, #0x40000000
+        FMXR    fpexc,r0
+        MOV     r0,#0x01000000
+        FMXR    fpscr,r0
+        BX      lr
+
+
+CPU_init_invalidate_tlb:
+        MOV         r2,#0
+        MCR         p15,0,r2,c8,c7,0 
+        MCR         p15,0,r2,c7,c10,4
+        BX          lr
+
+        .section .page_table,"a"
+        .align   14
+        .globl   CPU_init_page_table
+CPU_init_page_table:
+        .space  (0x1000 * 4)