Working boot (up to menu), USB might be broken

Makefile

@@ -1,4 +1,4 @@
-BOARDS ?= QUARTZ64 SOQUARTZ ROC-RK3566-PC ROC-RK3568-PC CORE3566
+BOARDS ?= CORE3566
 TARGET ?= RELEASE
 
 .PHONY: all

build.sh

@@ -14,7 +14,7 @@ export PACKAGES_PATH=$PWD/edk2:$PWD/edk2-platforms:$PWD/edk2-non-osi:$PWD/edk2-r
 export GCC5_AARCH64_PREFIX=aarch64-linux-gnu-
 
 TRUST_INI=RK3568TRUST.ini
-MINIALL_INI=RK3568MINIALL.ini
+MINIALL_INI=RK3566MINIALL.ini
 
 RKBIN=edk2-rockchip-non-osi/rkbin
 FIRMWARE_VER="$(git describe --tags --dirty)"

edk2-rockchip-non-osi/rkbin/RKBOOT/RK3566MINIALL.ini

@@ -5,7 +5,7 @@ MAJOR=1
 MINOR=1
 [CODE471_OPTION]
 NUM=1
-Path1=bin/rk35/rk3566_ddr_1056MHz_v1.11.bin
+Path1=bin/rk35/rk3566_ddr_324MHz_v1.11.bin
 Sleep=1
 [CODE472_OPTION]
 NUM=1
@@ -14,7 +14,7 @@ Path1=bin/rk35/rk356x_usbplug_v1.14.bin
 NUM=2
 LOADER1=FlashData
 LOADER2=FlashBoot
-FlashData=bin/rk35/rk3566_ddr_1056MHz_v1.11.bin
+FlashData=bin/rk35/rk3566_ddr_324MHz_v1.11.bin
 FlashBoot=bin/rk35/rk356x_spl_v1.12.bin
 [OUTPUT]
 PATH=rk356x_spl_loader_v1.11.112.bin

edk2-rockchip-non-osi/rkbin/RKBOOT/RK3568MINIALL.ini

@@ -5,7 +5,7 @@ MAJOR=1
 MINOR=1
 [CODE471_OPTION]
 NUM=1
-Path1=bin/rk35/rk3568_ddr_1560MHz_v1.11.bin
+Path1=bin/rk35/rk3568_ddr_324MHz_v1.11.bin
 Sleep=1
 [CODE472_OPTION]
 NUM=1
@@ -14,7 +14,7 @@ Path1=bin/rk35/rk356x_usbplug_v1.14.bin
 NUM=2
 LOADER1=FlashData
 LOADER2=FlashBoot
-FlashData=bin/rk35/rk3568_ddr_1560MHz_v1.11.bin
+FlashData=bin/rk35/rk3568_ddr_324MHz_v1.11.bin
 FlashBoot=bin/rk35/rk356x_spl_v1.12.bin
 [OUTPUT]
 PATH=rk356x_spl_loader_v1.11.112.bin

edk2-rockchip/Platform/Luckfox/Core3566/Core3566.dsc

@@ -287,7 +287,7 @@
 !if $(TARGET) == RELEASE
   gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
 !else
-  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0f
 !endif
 
   #  DEBUG_INIT      0x00000001  // Initialization
@@ -470,18 +470,20 @@
   gRk356xTokenSpaceGuid.PcdPciePowerGpioBank|0
   gRk356xTokenSpaceGuid.PcdPciePowerGpioPin|20
 
+  gRk356xTokenSpaceGuid.PcdMshcDxeMaxClockFreqInHz|10000000
+
   #
   # The Core3566 has a WiFi card on the second MSHC
   #
-  gRk356xTokenSpaceGuid.PcdMshc1Status|0xF
-  gRk356xTokenSpaceGuid.PcdMshc1SdioIrq|TRUE
-  gRk356xTokenSpaceGuid.PcdMshc1NonRemovable|TRUE
+  #gRk356xTokenSpaceGuid.PcdMshc1Status|0xF
+  #gRk356xTokenSpaceGuid.PcdMshc1SdioIrq|TRUE
+  #gRk356xTokenSpaceGuid.PcdMshc1NonRemovable|TRUE
 
   #
   # RTC support (hym8563 at 0x51 on I2C2)
   #
-  gRk356xTokenSpaceGuid.PcdRtcI2cBusBase|0xFE5B0000
-  gRk356xTokenSpaceGuid.PcdRtcI2cAddr|0x51
+  #gRk356xTokenSpaceGuid.PcdRtcI2cBusBase|0xFE5B0000
+  #gRk356xTokenSpaceGuid.PcdRtcI2cAddr|0x51
 
 
 [PcdsDynamicHii.common.DEFAULT]

edk2-rockchip/Platform/Luckfox/Core3566/Drivers/BoardInitDxe/BoardInitDxe.c

@@ -210,7 +210,7 @@ BoardInitPmic (
 
   DEBUG ((DEBUG_INFO, "BOARD: PMIC init\n"));
 
-  /* I2C2 bus, used for RTC */
+  /* I2C0 bus, used for PMIC */
   GpioPinSetPull (0, GPIO_PIN_PB1, GPIO_PIN_PULL_NONE);
   GpioPinSetInput (0, GPIO_PIN_PB1, GPIO_PIN_INPUT_SCHMITT);
   GpioPinSetFunction (0, GPIO_PIN_PB1, 1);
@@ -245,11 +245,11 @@ BoardInitPmic (
   PmicWrite (PMIC_LDO6_ON_VSEL, 0x6c);  /* 3.3V - vcc3v3_pmu */
   PmicWrite (PMIC_LDO7_ON_VSEL, 0x30);  /* 1.8V - vcca_1v8 */
   PmicWrite (PMIC_LDO8_ON_VSEL, 0x30);  /* 1.8V - vcca1v8_pmu */
-  PmicWrite (PMIC_LDO9_ON_VSEL, 0x30);  /* 1.8V - vcca1v8_image */
+  PmicWrite (PMIC_LDO9_ON_VSEL, 0x6c);  /* 3.3V - VCC_GPIO0_17 */
 
   PmicWrite (PMIC_POWER_EN1, 0xff); /* LDO1, LDO2, LDO3, LDO4 */
   PmicWrite (PMIC_POWER_EN2, 0xee); /* LDO6, LDO7, LDO8 */
-  PmicWrite (PMIC_POWER_EN3, 0x55); /* LDO9, SW1*/
+  PmicWrite (PMIC_POWER_EN3, 0xDD); /* LDO9, SW1, SW2*/
 }
 
 //STATIC
@@ -306,13 +306,13 @@ BoardInitDriverEntryPoint (
 //  GpioPinWrite (0, GPIO_PIN_PD3, TRUE);
 
   /* Enable automatic clock gating */
-  MmioWrite32 (PMU_NOC_AUTO_CON0, 0xFFFFFFFFU);
-  MmioWrite32 (PMU_NOC_AUTO_CON1, 0x000F000FU);
-
-  /* Set core_pvtpll ring length */
-  MmioWrite32 (GRF_CPU_COREPVTPLL_CON0,
-               ((CORE_PVTPLL_RING_LENGTH_SEL_MASK | CORE_PVTPLL_OSC_EN | CORE_PVTPLL_START) << 16) |
-               (5U << CORE_PVTPLL_RING_LENGTH_SEL_SHIFT) | CORE_PVTPLL_OSC_EN | CORE_PVTPLL_START);
+//  MmioWrite32 (PMU_NOC_AUTO_CON0, 0xFFFFFFFFU);
+//  MmioWrite32 (PMU_NOC_AUTO_CON1, 0x000F000FU);
+////
+////  /* Set core_pvtpll ring length */
+//  MmioWrite32 (GRF_CPU_COREPVTPLL_CON0,
+//               ((CORE_PVTPLL_RING_LENGTH_SEL_MASK | CORE_PVTPLL_OSC_EN | CORE_PVTPLL_START) << 16) |
+//               (5U << CORE_PVTPLL_RING_LENGTH_SEL_SHIFT) | CORE_PVTPLL_OSC_EN | CORE_PVTPLL_START);
 
 //  /* Configure MULTI-PHY 0 and 1 for USB3 mode */
 //  MultiPhySetMode (0, MULTIPHY_MODE_USB3);

edk2-rockchip/Silicon/Rockchip/Rk356x/Drivers/MshcDxe/MshcDxe.c

@@ -616,9 +616,16 @@ MshcWriteBlockData (
   ASSERT ((mMshcCommand & BIT_CMD_WRITE) == BIT_CMD_WRITE);
 
   if (mMshcCommand & BIT_CMD_WAIT_PRVDATA_COMPLETE) {
+    TimeOut = 100000;
     do {
       Data = MmioRead32 (DWEMMC_STATUS);
-    } while (Data & DWEMMC_STS_DATA_BUSY);
+      TimeOut--;
+    } while ((Data & DWEMMC_STS_DATA_BUSY) && (TimeOut > 0));
+
+    if (TimeOut == 0) {
+        DEBUG ((DEBUG_ERROR, "%a():  CMD=%d SDC_SDC_ERROR DWEMMC_STATUS DWEMMC_STS_DATA_BUSY\n", __func__, mMshcCommand&0x3f));
+        return EFI_DEVICE_ERROR;
+    }
   }
 
   if (!(((mMshcCommand&0x3f) == 6) || ((mMshcCommand&0x3f) == 51))) {
@@ -648,13 +655,25 @@ MshcWriteBlockData (
     DEBUG ((DEBUG_ERROR, "Failed to write data, mMshcCommand:%x, mMshcArgument:%x, Status:%r\n", mMshcCommand, mMshcArgument, Status));
     return EFI_DEVICE_ERROR;
   }
+
+  DEBUG ((DEBUG_ERROR, "%a():  CMD=%d send command done\n", __func__, mMshcCommand&0x3f));
 
   for (Count = 0; Count < Size32; Count++) {
-    while(MMC_GET_FCNT(MmioRead32(DWEMMC_STATUS)) >32)
-    MicroSecondDelay(1);
+    TimeOut = 100000;
+    while((MMC_GET_FCNT(MmioRead32(DWEMMC_STATUS)) >32) && (TimeOut > 0))
+    {
+      MicroSecondDelay(1);
+      TimeOut--;
+    }
+    if (TimeOut == 0) {
+        DEBUG ((DEBUG_ERROR, "%a():  CMD=%d MMC_GET_FCNT(MmioRead32(DWEMMC_STATUS) timeout\n", __func__, mMshcCommand&0x3f));
+        return EFI_DEVICE_ERROR;
+    }
     MmioWrite32(DWEMMC_DATA, *DataBuffer++);
   }
 
+  DEBUG ((DEBUG_ERROR, "%a():  CMD=%d data xfer done\n", __func__, mMshcCommand&0x3f));
+
   do {
     Mask = MmioRead32(DWEMMC_RINTSTS);
     if (Mask & (MMC_DATA_ERROR_FLAGS)) {
@@ -663,6 +682,9 @@ MshcWriteBlockData (
     }	
   } while (!(Mask & DWEMMC_INT_DTO));
 
+  DEBUG ((DEBUG_ERROR, "%a():  CMD=%d wait for interrupt done\n", __func__, mMshcCommand&0x3f));
+
+
   return EFI_SUCCESS;
 }