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1. cpe133_finalProject cpe133_finalProject Public

   Final project for CPE133. Whack-A-Mole game played on a Diligent BASYS-3 FPGA dev board.

   Verilog

2. cpe233_riscVmcu cpe233_riscVmcu Public

   Final project for CPE233. RISCV based mcu created for the Diligent BASYS-3 FPGA dev board.

   SystemVerilog

3. cpe333_pipelined-cached_riscVmcu cpe333_pipelined-cached_riscVmcu Public

   5-stage pipelined RISCV implementation with caching.

   SystemVerilog

4. ee329_finalProject ee329_finalProject Public

   Self-balancing robot code for stm32.

   C

5. VerilogComms VerilogComms Public

   Generic communication modules I created for FPGA.

   Verilog

6. QPSK_modulation QPSK_modulation Public

   QPSK demodulator for FPGA

   Verilog