111.949MHz/1A7C: UART, Font,

* A few adjustments and bugs fixes have been made to make the UART more
reliable. The clock has been changed slightly to more accurately reflect
the UART timing and frame errors are detected correctly. One extra stop
bit was being added/being required than should have been needed, this
has been fixed in configuration.
* The default font has been improved with a better character range, by
default KOI8-R encoded 8x12 terminus is used.
* The new graphics mode test code stuff has been removed, I cannot think
of a good way of adding this mode in without making everything much more
complicated, so I will leave it out for now.
* The image has shrunk slightly, and less memory is used in the
metacompiler.
* The ANSI test suite now works correctly when transferred over the UART.

Author: howerj

embed.fth

@@ -95,7 +95,8 @@ EFORTH=h2.hex
 h2${EXE}: h2.c h2.h
 	${CC} ${CFLAGS} -std=c99 $< -o $@
 
-embed${EXE}: embed.o
+embed${EXE}: embed.c
+	${CC} ${CFLAGS} -std=c99 $< -o $@
 
 ${EFORTH}: embed${EXE} embed.blk embed.fth
 	${DF}embed${EXE} embed.blk $@ embed.fth

font.bin

@@ -258,7 +258,10 @@ interface with devices on the [Nexys3][] board:
 * [VGA][] output device, text mode only, 80 by 40 characters from
   <http://www.javiervalcarce.eu/html/vhdl-vga80x40-en.html>. This has
 been heavily modified from the original, which now implements most of a
-[VT100][] terminal emulator.
+[VT100][] terminal emulator. This has two fonts available to it:
+  - [Terminus][]/[KOI8-R][] (Default)
+  - Latin [ISO-8859-15][] (Secondary Font) from
+  <https://git.kernel.org/pub/scm/linux/kernel/git/legion/kbd.git>
 * [Timer][] in [timer.vhd][].
 * [UART][] (Rx/Tx) in [uart.vhd][].
 * [PS/2][] Keyboard
@@ -1213,6 +1216,9 @@ a text buffer to it would help in developing code for the platform.
 [embed]: https://github.com/howerj/embed
 [SDL]: https://www.libsdl.org/
 [Apache 2.0]: https://www.apache.org/licenses/LICENSE-2.0.html
+[KOI8-R]: https://en.wikipedia.org/wiki/KOI8-R
+[Terminus]: http://terminus-font.sourceforge.net/
+[ISO-8859-15]: https://en.wikipedia.org/wiki/ISO/IEC_8859-15
 
 <!--
 

fonts/terminus.bin

@@ -11,7 +11,7 @@ WORDLIST CONSTANT COOL-TEXT ( <_< - way cool )
 COOL-TEXT >ORDER DEFINITIONS
 VARIABLE COOL-CHARACTER CHAR * COOL-CHARACTER !
 : BYE BYE ;
-: CR CR ;
+: CR $D EMIT $A EMIT ;
 : {{ CR COOL-TEXT >ORDER DUP ;
 : >_> CHAR COOL-CHARACTER ! ;
 : <_< [CHAR] * COOL-CHARACTER ! ;

makefile

@@ -39,14 +39,16 @@ architecture testing of tb is
 	);
 
 	constant number_of_interrupts:    positive := 8;
-	constant uart_baud:          positive := 115200;
+	constant uart_baud:               positive := 115200;
 	constant configuration_file_name: string   := "tb.cfg";
 	constant uart_tx_time:            time     := (10*1000 ms) / 115200;
 	constant uart_default_input:      std_ulogic_vector(7 downto 0) := x"AA";
 	constant reset_period_us:         natural  := 1;
 	constant jitter_on:               boolean  := false;
-
 	constant clock_period:            time     := 1000 ms / g.clock_frequency;
+	constant tb_vga_on:               boolean  := false;
+	constant tb_uart_on:              boolean  := false;
+	constant tb_util_on:              boolean  := false;
 
 	-- Test bench configurable options --
 
@@ -169,15 +171,11 @@ begin
 		mem_addr  =>  mem_addr,
 		mem_data  =>  mem_data);
 
-	uut_util: work.util.util_tb generic map(g => g);
-	uut_vga:  work.vga_pkg.vt100_tb generic map(g => g);
-
-	-- The "io_pins_tb" works correctly, however in GHDL 0.29, compiled under
-	-- Windows, fails to simulate this component correctly, resulting
-	-- in a crash. This does not affect the Linux build of GHDL. It has
-	-- something to do with 'Z' values for std_logic types.
-
-	uut_io_pins: work.util.io_pins_tb  generic map(g => g);
+	-- NB. It would be nice to configure these as off/on, as well as
+	-- controlling how long they run for from here.
+	util_g: if tb_util_on generate uut_util: work.util.util_tb     generic map(g => g); end generate;
+	vga_g:  if tb_vga_on  generate uut_vga:  work.vga_pkg.vt100_tb generic map(g => g); end generate;
+	uart_g: if tb_uart_on generate uut_uart: work.uart_pkg.uart_tb generic map(g => g); end generate;
 
 	uart_0_blk: block 
 		signal uart_clock_rx_we, uart_clock_tx_we, uart_control_we: std_ulogic := '0';

readme.md

@@ -75,6 +75,7 @@ architecture behav of top is
 	constant number_of_interrupts:   positive := 8;
 	constant number_of_led_displays: positive := 4;
 	constant timer_period_us:        positive := 20000;
+	constant use_sine:               boolean  := false;
 
 	-- Signals
 	signal rst:      std_ulogic := '0';
@@ -151,12 +152,9 @@ architecture behav of top is
 	signal mem_data_o:        std_ulogic_vector(15 downto 0) := (others => '0');
 	signal mem_control_we:    std_ulogic := '0';
 
---	signal sine_we: std_ulogic := '0';
---	signal sine: std_ulogic_vector(15 downto 0) := (others => '0');
+	signal sine_we: std_ulogic := '0';
+	signal sine: std_ulogic_vector(15 downto 0) := (others => '0');
 
-	signal vt100_raw_addr_we: std_ulogic := '0';
-	signal vt100_raw_data_we: std_ulogic := '0';
-	signal vt100_raw_do:      std_ulogic_vector(15 downto 0) := (others => '0');
 begin
 -------------------------------------------------------------------------------
 -- The Main components
@@ -170,6 +168,8 @@ begin
 		clk        => clk,
 		rst        => rst);
 
+	-- TODO: Add interrupts on video blanking periods, which should
+	-- make writing graphics code easier.
 	cpu_irc(0) <= btnu_d; -- configurable CPU reset (can mask this)
 	cpu_irc(1) <= not rx_fifo_empty;
 	cpu_irc(2) <= rx_fifo_full;
@@ -253,10 +253,9 @@ begin
 		uart_clock_rx_we  <= '1'         when is_write and selector = x"A" else '0';
 		uart_control_we   <= '1'         when is_write and selector = x"B" else '0';
 
---		sine_we           <= '1'         when is_write and selector = x"C" else '0';
-
-		vt100_raw_addr_we <= '1'         when is_write and selector = x"C" else '0';
-		vt100_raw_data_we <= '1'         when is_write and selector = x"D" else '0';
+		sine_o: if use_sine generate
+		sine_we           <= '1'         when is_write and selector = x"C" else '0';
+		end generate;
 	end block;
 
 	io_read: process(
@@ -274,8 +273,7 @@ begin
 		timer_counter_o,
 
 		vga_data_busy,
-		vt100_raw_do,
---		sine,
+		sine,
 
 		mem_data_o)
 	begin
@@ -304,30 +302,21 @@ begin
 		when "100" =>
 			io_din             <= mem_data_o;
 		when "101" =>
-			io_din             <= vt100_raw_do;
-			-- io_din             <= sine;
+			if use_sine then
+				io_din <= sine;
+			end if;
 		when others => io_din <= (others => '0');
 		end case;
 	end process;
 
 	--- Sine ----------------------------------------------------------
--- 	sine_block: block
--- 		signal x, s: std_ulogic_vector(15 downto 0);
--- 	begin
--- 		reg_sin: work.util.reg 
--- 			generic map(g => g, N => x'length) 
--- 			port map(clk => clk, rst => rst, we => sine_we, di => io_dout, do => x);
--- 
--- 		sine_fifo_0: work.util.sine generic map(g => g) port map(x => x, s => s);
--- 
--- 		reg_sout: work.util.reg 
--- 			generic map(g => g, N => x'length) 
--- 			port map(clk => clk, rst => rst, we => '1', di => s, do => sine);
--- 
--- 	end block;
+	sine_gen_0: if use_sine generate
+		sine_0: work.util.sine 
+			generic map(g => g) 
+			port map(clk => clk, rst => rst, xwe => sine_we, x => io_dout, s => sine);
+	end generate;
 	--- Sine ----------------------------------------------------------
 
-
 	--- UART ----------------------------------------------------------
 	uart_fifo_0: work.uart_pkg.uart_top
 		generic map (g => g, baud => uart_baud, use_fifo => false)
@@ -390,12 +379,7 @@ begin
 				we          =>  vga_data_we,
 				char        =>  vga_data,
 				busy        =>  vga_data_busy,
-				o_vga       =>  o_vga,
-			
-				raw_addr_we =>  vt100_raw_addr_we,
-				raw_data_we =>  vt100_raw_data_we,
-				raw_di      =>  io_dout,
-				raw_do      =>  vt100_raw_do);
+				o_vga       =>  o_vga);
 		end generate;
 
 		-- Test code

t/ansi.fth

@@ -1,4 +1,4 @@
---
+-- FILE:      uart.vhd
 -- BRIEF:     UART TX/RX module
 -- LICENSE:   MIT
 -- COPYRIGHT: Richard James Howe (2019)
@@ -323,38 +323,44 @@ architecture structural of uart_core is
 	signal rx_fail: std_ulogic_vector(1 downto 0);
 	signal rx_ok_buf: std_ulogic;
 	signal do, do_c, do_n: std_ulogic_vector(rx_do'range);
+	signal fail_c, fail_n: std_ulogic_vector(1 downto 0);
 	signal nd_c, nd_n: std_ulogic; -- new data
 begin 
-	rx_ok_buf <= not (rx_fail(0) or rx_fail(1)) after g.delay;
-	rx_ok <= rx_ok_buf after g.delay;
+	rx_ok_buf <= not (fail_c(0) or fail_c(1)) after g.delay;
+	rx_ok <= rx_ok_buf;
 	rx_do <= do after g.delay;
 	rx_nd <= nd_c and rx_ok_buf after g.delay; -- no new data if there are errors
 
 	process (clk, rst) 
 	begin
 		if rst = '1' and g.asynchronous_reset then
-			do_c <= (others => '0') after g.delay;
-			nd_c <= '0' after g.delay;
+			do_c   <= (others => '0') after g.delay;
+			fail_c <= (others => '0') after g.delay;
+			nd_c   <= '0' after g.delay;
 		elsif rising_edge(clk) then
 			if rst = '1' and not g.asynchronous_reset then
-				do_c <= (others => '0') after g.delay;
-				nd_c <= '0' after g.delay;
+				do_c   <= (others => '0') after g.delay;
+				fail_c <= (others => '0') after g.delay;
+				nd_c   <= '0' after g.delay;
 			else
-				do_c <= do_n after g.delay;
-				nd_c <= nd_n after g.delay;
+				do_c <= do_n     after g.delay;
+				nd_c <= nd_n     after g.delay;
+				fail_c <= fail_n after g.delay;
 			end if;
 		end if;
 	end process;
 
-	process (do_c, do, nd_c, rx_we, rx_re) 
+	process (do_c, do, nd_c, rx_we, rx_re, fail_c, rx_fail) 
 	begin
-		do_n <= do_c after g.delay;
-		nd_n <= nd_c after g.delay;
+		do_n   <= do_c   after g.delay;
+		nd_n   <= nd_c   after g.delay;
+		fail_n <= fail_c after g.delay; 
 		if rx_we = '1' then
-			do_n <= do after g.delay;
-			nd_n <= '1' after g.delay;
+			nd_n   <= '1'     after g.delay;
+			do_n   <= do      after g.delay;
+			fail_n <= rx_fail after g.delay;
 		elsif rx_re = '1' then
-			nd_n <= '0' after g.delay;
+			nd_n   <= '0' after g.delay;
 		end if;
 	end process;
 
@@ -608,7 +614,7 @@ begin
 			state_n  <= idle after g.delay;
 		when idle =>
 			count_n <= 0 after g.delay;
-			if rx_sync = '0' and majority = '1' then
+			if rx_sync = '0' then -- and majority = '1' then
 				state_n <= start after g.delay;
 				cr      <= '1' after g.delay;
 				sr_n    <= (others => '0') after g.delay;
@@ -653,7 +659,6 @@ begin
 					state_n   <= done after g.delay; -- frame error
 					fail_n(0) <= '1' after g.delay;
 				elsif count_c = ctr_stop_bits(ctr_c) then
-					count_n <= 0 after g.delay;
 					state_n <= done after g.delay;
 				else
 					count_n <= count_c + 1 after g.delay;
@@ -662,6 +667,9 @@ begin
 		when done => -- The consuming module needs to store rx_c/fail_c immediately
 			we      <= '1' after g.delay;
 			state_n <= idle after g.delay;
+			--rx_n    <= (others => '0') after g.delay;
+			--sr_n    <= (others => '0') after g.delay;
+			--fail_n  <= (others => '0') after g.delay;
 		end case;
 
 		if ctr_we = '1' then
@@ -817,11 +825,17 @@ architecture testing of uart_tb is
 	constant clock_period: time     := 1000 ms / g.clock_frequency;
 	signal rst, clk:     std_ulogic := '1';
 	signal stop:         boolean    := false;
+	signal loopback:     boolean    := true;
 	signal tx, rx:       std_ulogic;
 	signal tx_ok, rx_ok: std_ulogic;
 	signal tx_we, rx_re: std_ulogic := '0';
 	signal rx_nd:        std_ulogic;
 	signal di, do:       std_ulogic_vector(7 downto 0);
+
+	signal reg:          std_ulogic_vector(15 downto 0);
+	signal clock_reg_tx_we: std_ulogic;
+	signal clock_reg_rx_we: std_ulogic;
+	signal control_reg_we:  std_ulogic;
 begin
 	-- duration: process begin wait for 20000 us; stop <= true; wait; end process;
 	clk_process: process
@@ -843,7 +857,7 @@ begin
 	stimulus: process 
 		procedure write(data: std_ulogic_vector(di'range)) is
 		begin
-			wait for clock_period;
+			wait for clock_period * 1;
 			while tx_ok = '0' loop
 				wait for clock_period;
 			end loop;
@@ -856,6 +870,19 @@ begin
 		di <= x"00";
 		wait until rst = '0';
 		wait for clock_period;
+		reg             <=  x"8080";
+		control_reg_we  <=  '1';
+		wait for clock_period;
+		control_reg_we  <=  '0';
+		reg             <=  x"0036";
+		clock_reg_tx_we <=  '1';
+		wait for clock_period;
+		clock_reg_tx_we <=  '0';
+		clock_reg_rx_we <=  '1';
+		reg             <=  x"0035";
+		wait for clock_period;
+		clock_reg_rx_we <=  '0';
+		wait for clock_period;
 
 		write(x"AA");
 		write(x"BB");
@@ -866,7 +893,8 @@ begin
 		while tx_ok = '0' loop
 			wait for clock_period;
 		end loop;
-
+		loopback <= false;
+		wait for clock_period * 50000;
 		stop <= true;
 		wait;
 	end process;
@@ -884,7 +912,7 @@ begin
 		wait;
 	end process;
 
-	rx <= tx; -- loop back test
+	rx <= tx when loopback else '0'; -- loop back test
 
 	uut: work.uart_pkg.uart_core
 		generic map(g => g)
@@ -900,10 +928,10 @@ begin
 			rx_nd           =>  rx_nd,
 			rx_re           =>  rx_re,
 			rx_do           =>  do,
-			reg             =>  (others => '0'),
-			clock_reg_tx_we =>  '0',
-			clock_reg_rx_we =>  '0',
-			control_reg_we  =>  '0'
+			reg             =>  reg,
+			clock_reg_tx_we =>  clock_reg_tx_we,
+			clock_reg_rx_we =>  clock_reg_rx_we,
+			control_reg_we  =>  control_reg_we 
 		);
 end architecture;