99.792MHz/1A82: Added control lines for raw mode

Control registers and lines for a raw mode, in which the programmer can
write to video memory directly, have been added. The idea is that they
will be able to use this mode for drawing on a low resolution display.

Author: howerj

top.vhd

@@ -66,8 +66,8 @@ entity top is
 		mem_wait:  out   std_ulogic := '0'; -- positive logic!
 		flash_cs:  out   std_ulogic := '0';
 		flash_rp:  out   std_ulogic := '1';
-		mem_addr:   out   std_ulogic_vector(26 downto 1) := (others => '0');
-		mem_data:    inout std_logic_vector(15 downto 0)  := (others => 'Z'));
+		mem_addr:  out   std_ulogic_vector(26 downto 1) := (others => '0');
+		mem_data:  inout std_logic_vector(15 downto 0)  := (others => 'Z'));
 end;
 
 architecture behav of top is
@@ -150,6 +150,13 @@ architecture behav of top is
 	signal mem_data_i_we:     std_ulogic := '0';
 	signal mem_data_o:        std_ulogic_vector(15 downto 0) := (others => '0');
 	signal mem_control_we:    std_ulogic := '0';
+
+--	signal sine_we: std_ulogic := '0';
+--	signal sine: std_ulogic_vector(15 downto 0) := (others => '0');
+
+	signal vt100_raw_addr_we: std_ulogic := '0';
+	signal vt100_raw_data_we: std_ulogic := '0';
+	signal vt100_raw_do:      std_ulogic_vector(15 downto 0) := (others => '0');
 begin
 -------------------------------------------------------------------------------
 -- The Main components
@@ -245,6 +252,11 @@ begin
 		uart_clock_tx_we  <= '1'         when is_write and selector = x"9" else '0';
 		uart_clock_rx_we  <= '1'         when is_write and selector = x"A" else '0';
 		uart_control_we   <= '1'         when is_write and selector = x"B" else '0';
+
+--		sine_we           <= '1'         when is_write and selector = x"C" else '0';
+
+		vt100_raw_addr_we <= '1'         when is_write and selector = x"C" else '0';
+		vt100_raw_data_we <= '1'         when is_write and selector = x"D" else '0';
 	end block;
 
 	io_read: process(
@@ -262,6 +274,8 @@ begin
 		timer_counter_o,
 
 		vga_data_busy,
+		vt100_raw_do,
+--		sine,
 
 		mem_data_o)
 	begin
@@ -289,10 +303,31 @@ begin
 			io_din <= "000" & btnu_d & btnd_d & btnl_d & btnr_d & btnc_d & sw_d;
 		when "100" =>
 			io_din             <= mem_data_o;
+		when "101" =>
+			io_din             <= vt100_raw_do;
+			-- io_din             <= sine;
 		when others => io_din <= (others => '0');
 		end case;
 	end process;
 
+	--- Sine ----------------------------------------------------------
+-- 	sine_block: block
+-- 		signal x, s: std_ulogic_vector(15 downto 0);
+-- 	begin
+-- 		reg_sin: work.util.reg 
+-- 			generic map(g => g, N => x'length) 
+-- 			port map(clk => clk, rst => rst, we => sine_we, di => io_dout, do => x);
+-- 
+-- 		sine_fifo_0: work.util.sine generic map(g => g) port map(x => x, s => s);
+-- 
+-- 		reg_sout: work.util.reg 
+-- 			generic map(g => g, N => x'length) 
+-- 			port map(clk => clk, rst => rst, we => '1', di => s, do => sine);
+-- 
+-- 	end block;
+	--- Sine ----------------------------------------------------------
+
+
 	--- UART ----------------------------------------------------------
 	uart_fifo_0: work.uart_pkg.uart_top
 		generic map (g => g, baud => uart_baud, use_fifo => false)
@@ -355,7 +390,12 @@ begin
 				we          =>  vga_data_we,
 				char        =>  vga_data,
 				busy        =>  vga_data_busy,
-				o_vga       =>  o_vga);
+				o_vga       =>  o_vga,
+			
+				raw_addr_we =>  vt100_raw_addr_we,
+				raw_data_we =>  vt100_raw_data_we,
+				raw_di      =>  io_dout,
+				raw_do      =>  vt100_raw_do);
 		end generate;
 
 		-- Test code

util.vhd

@@ -3963,6 +3963,9 @@ end architecture;
 -- Angles are input as signed Furmans (1 Furman = (1/pow(2, 16) of a circle))
 -- 1 Degree is ~182 Furmans. 1 rad is ~10430 Furmans.
 -- Result is signed scaled 16-bit integer; -1 = -32767, +1 = 32767
+--
+-- TODO: Optionally insert registers at various locations throughout the module, specified
+-- with a generic.
 library ieee, work;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -4065,3 +4068,5 @@ begin
 		wait;
 	end process;
 end architecture;
+------------------------- Sine / Cosine  ------------------------------------------------------
+

vga.vhd

@@ -50,7 +50,7 @@ package vga_pkg is
 	type vga_control_registers_interface is record
 		crx:    std_ulogic_vector(6 downto 0); -- Cursor position X
 		cry:    std_ulogic_vector(5 downto 0); -- Cursor position Y
-		ctl:    std_ulogic_vector(4 downto 0); -- Control register
+		ctl:    std_ulogic_vector(5 downto 0); -- Control register
 	end record;
 
 	constant vga_control_registers_initialize: vga_control_registers_interface := (
@@ -75,6 +75,7 @@ package vga_pkg is
 		vga_din:     in  std_ulogic_vector(15 downto 0);
 		vga_addr:    in  std_ulogic_vector(12 downto 0);
 		base:        in  std_ulogic_vector(12 downto 0);
+		raw_do:      out  std_ulogic_vector(15 downto 0);
 
 		-- VGA control registers
 		i_font_sel:       in std_ulogic_vector(0 downto 0);
@@ -97,7 +98,7 @@ package vga_pkg is
 		 --
 		ocrx:      in  std_ulogic_vector(6 downto 0);
 		ocry:      in  std_ulogic_vector(5 downto 0);
-		octl:      in  std_ulogic_vector(4 downto 0);
+		octl:      in  std_ulogic_vector(5 downto 0);
 		--
 		o_vga: out vga_physical_interface);
 	end component;
@@ -134,7 +135,12 @@ package vga_pkg is
 		char:       in  std_ulogic_vector(7 downto 0);
 
 		busy:       out std_ulogic;
-		o_vga:      out vga_physical_interface);
+		o_vga:      out vga_physical_interface;
+	
+		raw_addr_we: in std_ulogic;
+		raw_data_we: in std_ulogic;
+		raw_di:      in std_ulogic_vector(15 downto 0);
+		raw_do:     out std_ulogic_vector(15 downto 0));
 	end component;
 
 	-- VGA test bench, not-synthesizeable
@@ -217,7 +223,12 @@ begin
 		we       => we,
 		char     => char,
 		busy     => busy,
-		o_vga    => physical);
+		o_vga    => physical,
+	
+		raw_addr_we => '0',
+		raw_data_we => '0',
+		raw_di      => x"0000",
+		raw_do      => open);
 
 	stimulus_process: process
 	begin
@@ -395,7 +406,12 @@ entity vt100 is
 		char:       in  std_ulogic_vector(7 downto 0);
 
 		busy:       out std_ulogic;
-		o_vga:      out vga_physical_interface);
+		o_vga:      out vga_physical_interface;
+		
+		raw_addr_we: in std_ulogic;
+		raw_data_we: in std_ulogic;
+		raw_di:      in std_ulogic_vector(15 downto 0);
+		raw_do:     out std_ulogic_vector(15 downto 0));
 end entity;
 
 -- A better way of structuring this would be to process numbers in parallel
@@ -424,7 +440,7 @@ architecture rtl of vt100 is
 	constant lsqb:         unsigned(char'range) := x"5b"; -- '['
 	constant ascii_c:      unsigned(char'range) := x"63"; -- 'c'
 	constant attr_default: unsigned(7 downto 0) := "00111000";
-	constant ctl_default:  unsigned(4 downto 0) := "01111";
+	constant ctl_default:  unsigned(5 downto 0) := "001111";
 
 	signal addr:           std_ulogic_vector(12 downto 0) := (others => '0');
 	signal data_we:        std_ulogic                     := '0';
@@ -479,7 +495,23 @@ architecture rtl of vt100 is
 
 	signal saved_base_n, saved_base_c: unsigned(base_c'range) := (others => '0');
 	signal is_base_saved_n, is_base_saved_c: boolean := false;
+
+	signal raw_addr: std_ulogic_vector(addr'range)   := (others => '0');
+	signal raw_data: std_ulogic_vector(raw_di'range) := (others => '0');
+	signal raw_data_we_delayed: std_ulogic := '0';
 begin
+	raw_data_reg: work.util.reg
+		generic map(g => g, N => raw_di'length)
+		port map(clk => clk, rst => rst, di => raw_di, we => raw_data_we, do => raw_data);
+	raw_addr_reg_we: work.util.reg
+		generic map(g => g, N => 1)
+		port map(clk => clk, rst => rst, di(0) => raw_addr_we, we => '1', do(0) => raw_data_we_delayed);
+
+	-- NB. Auto increment feature on addr might be useful
+	raw_addr_reg: work.util.reg
+		generic map(g => g, N => raw_addr'length)
+		port map(clk => clk, rst => rst, di => raw_di(raw_addr'range), we => raw_addr_we, do => raw_addr);
+
 	accumulator_0: work.vga_pkg.atoi
 		generic map(g => g, N => number)
 		port map(
@@ -496,11 +528,13 @@ begin
 	address: block
 		signal mul: unsigned(15 downto 0)     := (others => '0');
 		signal addr_int: unsigned(addr'range) := (others => '0');
+		signal addr_cooked: std_ulogic_vector(addr'range) := (others => '0');
 	begin
 		mul      <= to_unsigned(to_integer(y_c) * width, mul'length);
 		addr_int <= mul(addr_int'range) + ("000000" & x_c);
 		addr_sel <= addr_int when state_c /= ERASING else count_c;
-		addr     <= std_ulogic_vector(addr_sel + (base_c & "0000"));
+		addr_cooked <= std_ulogic_vector(addr_sel + (base_c & "0000"));
+		addr     <= addr_cooked when ctl_c(5) = '0' else raw_addr;
 	end block;
 
 	x_minus_one         <= x_c - 1;
@@ -531,28 +565,31 @@ begin
 		signal vga_ctr:    vga_control_registers_interface    := vga_control_registers_initialize;
 		signal attr:       unsigned(attr_c'range)             := attr_default;
 		signal ch:         std_ulogic_vector(c_c'range)       := (others => '0');
+		signal top_we:     std_ulogic                         := '0';
 	begin
 		ch             <= std_ulogic_vector(asterisk) when conceal_c else std_ulogic_vector(c_c);
 		attr           <= attr_c when state_c /= ERASING else attr_default;
-		vga_din        <= std_ulogic_vector(attr) & ch;
+		vga_din        <= std_ulogic_vector(attr) & ch when ctl_c(5) = '0' else raw_data;
 		vga_ctr.crx    <= std_ulogic_vector(x_plus_one); -- not limited, goes off screen edge
 		vga_ctr.cry    <= std_ulogic_vector(y_c);
 		vga_ctr.ctl    <= std_ulogic_vector(ctl_c);
 		vga_ctr_we.crx <= cursor_we;
 		vga_ctr_we.cry <= cursor_we;
 		vga_ctr_we.ctl <= cursor_we;
+		top_we         <= data_we when ctl_c(5) = '0' else raw_data_we_delayed;
 
 		vga_0: work.vga_pkg.vga_top
 		generic map(g => g)
 		port map(
 			clk               =>  clk,
 			clk25MHz          =>  clk25MHz,
 			rst               =>  rst,
-			vga_we_ram        =>  data_we,
+			vga_we_ram        =>  top_we,
 			vga_din           =>  vga_din,
 			vga_addr          =>  addr,
 			base(base_c'range)=>  std_ulogic_vector(base_c),
 			base(3 downto 0)  =>  "0000",
+			raw_do            =>  raw_do,
 			i_font_sel        =>  font_sel_c,
 			i_vga_control_we  =>  vga_ctr_we,
 			i_vga_control     =>  vga_ctr,
@@ -762,6 +799,15 @@ begin
 					when x"6d" => -- CSI n 'm' : SGR
 						state_n <= ATTRIB;
 
+					when x"68" =>
+						if n1_c = X"02" then -- 80x40 (in MS-DOS it is 80x25)
+							ctl_n(5) <= '0';
+						elsif n1_c = X"05" then -- 320x200 monochrome
+							ctl_n(5) <= '1';
+						else
+							-- unsupported mode
+						end if;
+						state_n <= ACCEPT;
 					-- NB. Number parameter does nothing.
 					when x"53" => -- CSI n 'S' : scroll up
 						saved_base_n <= base_c;
@@ -903,6 +949,7 @@ begin
 					when x"2D"  => reverse_video("101", false); 
 					when x"2E"  => reverse_video("110", false); 
 					when x"2F"  => reverse_video("111", false); 
+
 					when others =>
 					end case;
 					state_n <= ACCEPT;
@@ -938,6 +985,7 @@ entity vga_top is
 		vga_din:          in  std_ulogic_vector(15 downto 0);
 		vga_addr:         in  std_ulogic_vector(12 downto 0);
 		base:             in  std_ulogic_vector(12 downto 0);
+		raw_do:          out  std_ulogic_vector(15 downto 0);
 
 		-- VGA control registers
 		i_font_sel:       in std_ulogic_vector(0 downto 0);
@@ -1039,7 +1087,7 @@ begin
 		a_dre   => '1',
 		a_addr  => vga_addr,
 		a_din   => vga_din,
-		a_dout  => open,
+		a_dout  => raw_do,
 		-- Internal interface
 		b_clk   => clk25MHz,
 		b_dwe   => '0',
@@ -1087,7 +1135,7 @@ entity vga_core is
 		--
 		ocrx:     in  std_ulogic_vector(6 downto 0);
 		ocry:     in  std_ulogic_vector(5 downto 0);
-		octl:     in  std_ulogic_vector(4 downto 0);
+		octl:     in  std_ulogic_vector(5 downto 0);
 		--
 		o_vga:    out vga_physical_interface);
 end entity;
@@ -1126,12 +1174,15 @@ architecture rtl of vga_core is
 
 	signal bell_c, bell_n: std_ulogic := '0';
 	signal bell_on_c, bell_on_n: std_ulogic := '0';
+
+	signal raw_mode: std_ulogic := '0';
 begin
 	-- Control register. Individual control signal
 	bell_n    <= octl(4);
 	bell      <= bell_c xor bell_n;
 	vga_en    <= octl(3);
-	cur_en    <= octl(2);
+	raw_mode  <= octl(5);
+	cur_en    <= octl(2) and not raw_mode;
 	cur_blink <= octl(1);
 	cur_mode  <= octl(0);
 
@@ -1205,7 +1256,7 @@ begin
 	-- Proboscide99 31/08/08
 	blank <= '0' when (hctr < 8) or (hctr > 647) or (vctr > 479) else '1';
 
-	-- flip-flips for sync of R, G y B signal, initialized with '0'
+	-- flip-flops for sync of R, G y B signal, initialized with '0'
 	process (rst, clk25MHz)
 	begin
 		if rst = '1' and g.asynchronous_reset then