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ZSTD decoder: cocotb utils and decoder testcases, verilog helper modules #3035
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2dca4ce
Add a separate test case for each test file
rw1nkler 53571ca
Add "pytype binary, library" hint
sgizler af3b51a
Add cocotb tests
koblonczek 11a248d
xls/modules/zstd: expose fifo verilog module
lpawelcz e0856b5
modules/zstd/cocotb: Add ZSTD frame generator library
lpawelcz a0a309f
dependency_support: Add zstandard python library
lpawelcz bffd3a3
modules/zstd: Add verilog simulation of the ZstdDecoder
lpawelcz de73006
Use frame generator in tests
koblonczek 5b6d804
modules/zstd/zstd_dec: Write decoded data to the memory
lpawelcz 03aef2a
modules/zstd/zstd_dec: Remove stream-based output interface
lpawelcz 9adb781
modules/zstd/zstd_dec_cocotb_test: Improve Verilog simulation
lpawelcz eaeb6ed
modules/zstd/memory/mem_writer: Reduce the amount of random test cases
lpawelcz fa09c1f
modules/zstd/memory: Move verilog sources to rtl subdirectory
lpawelcz e3e64bd
xls/modules/zstd/external: Add docstring and license for third party …
lpawelcz bcaf1c5
modules/zstd: Adjust cocotb test to removal of RESET CSR
lpawelcz 7153a6a
Style changes
wsipak aa24e64
Extend cocotb tests of ZSTD decoder
rw1nkler be24b01
Collect P&R benchmarks
rw1nkler 5e90234
Add fixed version of RamDemux together with a test
rw1nkler 49116aa
Document decoder testing
sgizler 8cc9a8e
dependency_support: Add verilog_axi package
rw1nkler e27ac0b
Use bazel package with verilog_axi
rw1nkler 3392904
Downgrade dependencies
rw1nkler e860acf
Run tests selectively in GitHub CI
rw1nkler 978cb54
Remove zstandard python library
rw1nkler aac3756
modules: zstd: update readme
rw1nkler a914314
Add cocotb check for verifying huffman codes
rw1nkler 1a5df3b
modules: zstd: cocotb: drop unused testcase
rw1nkler 0393f5b
modules: zstd: disable huffman code builder PnR
rw1nkler 86d2c87
modules: zstd: fix formatting
rw1nkler acf0ffd
Update python lock file
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15 changes: 15 additions & 0 deletions
15
dependency_support/com_github_alexforencich_verilog_axi/BUILD.bazel
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Original file line number | Diff line number | Diff line change |
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# Copyright 2025 The XLS Authors | ||
# | ||
# Licensed under the Apache License, Version 2.0 (the "License"); | ||
# you may not use this file except in compliance with the License. | ||
# You may obtain a copy of the License at | ||
# | ||
# http://www.apache.org/licenses/LICENSE-2.0 | ||
# | ||
# Unless required by applicable law or agreed to in writing, software | ||
# distributed under the License is distributed on an "AS IS" BASIS, | ||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
# See the License for the specific language governing permissions and | ||
# limitations under the License. | ||
|
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# Needed to make this a package. |
45 changes: 45 additions & 0 deletions
45
dependency_support/com_github_alexforencich_verilog_axi/bundled.BUILD.bazel
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,45 @@ | ||
# Copyright 2025 The XLS Authors | ||
# | ||
# Licensed under the Apache License, Version 2.0 (the "License"); | ||
# you may not use this file except in compliance with the License. | ||
# You may obtain a copy of the License at | ||
# | ||
# http://www.apache.org/licenses/LICENSE-2.0 | ||
# | ||
# Unless required by applicable law or agreed to in writing, software | ||
# distributed under the License is distributed on an "AS IS" BASIS, | ||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
# See the License for the specific language governing permissions and | ||
# limitations under the License. | ||
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load("@xls_pip_deps//:requirements.bzl", "requirement") | ||
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package(default_visibility = ["//visibility:public"]) | ||
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exports_files( | ||
glob(["rtl/*.v"]), | ||
) | ||
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py_binary( | ||
name = "axi_crossbar_wrap", | ||
srcs = ["rtl/axi_crossbar_wrap.py"], | ||
deps = [requirement("Jinja2")], | ||
) | ||
|
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py_binary( | ||
name = "axi_interconnect_wrap", | ||
srcs = ["rtl/axi_interconnect_wrap.py"], | ||
deps = [requirement("Jinja2")], | ||
) | ||
|
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py_binary( | ||
name = "axil_crossbar_wrap", | ||
srcs = ["rtl/axi_crossbar_wrap.py"], | ||
deps = [requirement("Jinja2")], | ||
) | ||
|
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py_binary( | ||
name = "axil_interconnect_wrap", | ||
srcs = ["rtl/axil_interconnect_wrap.py"], | ||
deps = [requirement("Jinja2")], | ||
) |
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I don't think there is a precedent for our project to import SystemVerilog third_party dependency, I'll have to figure out how to make this work.
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as we discussed, it might be worth exploring landing the verilog dependency in a separate PR (and merge first the cocotb tests that don't depend on it)