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Bump LiteX and other dependencies. #743

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Bump LiteX and other dependencies. #743

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1935162
Bump LiteX and other dependencies.
Nov 29, 2022
58407b1
Add -I$(LIBC_DIR)/tinystdio to build flags.
Nov 29, 2022
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2 changes: 1 addition & 1 deletion third_party/python/amaranth
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Submodule amaranth updated 16 files
+3 −2 .github/workflows/main.yaml
+3 −2 amaranth/_toolchain/cxx.py
+5 −0 amaranth/back/rtlil.py
+18 −10 amaranth/build/plat.py
+93 −53 amaranth/hdl/ast.py
+4 −3 amaranth/lib/coding.py
+64 −37 amaranth/sim/_pyrtl.py
+5 −8 amaranth/vendor/intel.py
+5 −7 amaranth/vendor/lattice_ecp5.py
+10 −19 amaranth/vendor/lattice_ice40.py
+5 −7 amaranth/vendor/lattice_machxo_2_3l.py
+6 −4 amaranth/vendor/xilinx.py
+1 −1 docs/lang.rst
+2 −1 docs/tutorial.rst
+62 −6 tests/test_hdl_ast.py
+8 −0 tests/test_sim.py
2 changes: 1 addition & 1 deletion third_party/python/jinja
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Submodule jinja updated 12 files
+1 −1 .github/workflows/tests.yaml
+5 −5 .pre-commit-config.yaml
+2 −2 docs/api.rst
+1 −1 docs/integration.rst
+2 −2 docs/switching.rst
+4 −2 docs/templates.rst
+11 −15 requirements/dev.txt
+8 −8 requirements/docs.txt
+2 −2 requirements/tests.txt
+2 −2 requirements/typing.txt
+4 −4 src/jinja2/environment.py
+11 −14 src/jinja2/loaders.py
2 changes: 1 addition & 1 deletion third_party/python/litedram
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Submodule litedram updated 8 files
+1 −1 .github/workflows/ci.yml
+3 −4 CONTRIBUTORS
+12 −11 litedram/frontend/axi.py
+1 −0 litedram/phy/__init__.py
+469 −0 litedram/phy/gw2ddrphy.py
+4 −6 litedram/phy/model.py
+1 −1 test/test_axi.py
+1 −0 test/test_lpddr5.py
2 changes: 1 addition & 1 deletion third_party/python/liteeth
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Submodule liteeth updated 7 files
+1 −1 .github/workflows/ci.yml
+1 −1 CONTRIBUTORS
+19 −0 examples/axi-lite-mii.yml
+5 −1 liteeth/common.py
+12 −8 liteeth/frontend/stream.py
+29 −9 liteeth/gen.py
+10 −4 liteeth/phy/k7_1000basex.py
2 changes: 1 addition & 1 deletion third_party/python/litepcie
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Submodule litepcie updated 8 files
+1 −1 .github/workflows/ci.yml
+1 −1 CONTRIBUTORS
+53 −30 litepcie/frontend/dma.py
+10 −11 litepcie/gen.py
+41 −61 litepcie/software/kernel/config.h
+1 −1 litepcie/software/kernel/liteuart.c
+8 −1 litepcie/software/kernel/main.c
+4 −4 litepcie/software/user/litepcie_test.c
2 changes: 1 addition & 1 deletion third_party/python/litescope
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Submodule litescope updated 2 files
+1 −1 .github/workflows/ci.yml
+2 −1 CONTRIBUTORS
2 changes: 1 addition & 1 deletion third_party/python/litespi
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Submodule litespi updated 4 files
+1 −1 .github/workflows/ci.yml
+2 −1 CONTRIBUTORS
+198 −0 litespi/gen.py
+5 −0 setup.py
2 changes: 1 addition & 1 deletion third_party/python/litex
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Submodule litex updated 146 files
2 changes: 1 addition & 1 deletion third_party/python/litex_boards
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Submodule litex_boards updated 258 files
2 changes: 1 addition & 1 deletion third_party/python/markupsafe
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Submodule markupsafe updated 2 files
+1 −1 .github/workflows/build.yaml
+1 −1 .github/workflows/tests.yaml
2 changes: 1 addition & 1 deletion third_party/python/migen
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Submodule migen updated 2 files
+355 −0 migen/build/platforms/digilent_genesys2.py
+2 −0 migen/build/xilinx/vivado.py
2 changes: 1 addition & 1 deletion third_party/python/pythondata-software-picolibc
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Submodule pythondata-software-picolibc updated 2 files
+14 −13 pythondata_software_picolibc/__init__.py
+1 −1 pythondata_software_picolibc/data
2 changes: 1 addition & 1 deletion third_party/python/pythondata_cpu_vexriscv
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Submodule pythondata_cpu_vexriscv updated 20 files
+1,148 −1,191 pythondata_cpu_vexriscv/verilog/VexRiscv.v
+1,236 −1,258 pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v
+1,241 −1,274 pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v
+9 −9 pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v
+9 −9 pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v
+1,351 −1,371 pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v
+1,567 −1,477 pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v
+1,663 −1,559 pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v
+1,493 −1,535 pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v
+1,570 −1,619 pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v
+1,484 −1,520 pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v
+937 −1,015 pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v
+1,006 −1,079 pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v
+1,007 −1,080 pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebugHwBP.v
+857 −895 pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v
+928 −969 pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v
+929 −970 pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebugHwBP.v
+2,697 −4,952 pythondata_cpu_vexriscv/verilog/VexRiscv_Secure.v
+2,805 −5,047 pythondata_cpu_vexriscv/verilog/VexRiscv_SecureDebug.v
+23 −1 pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala