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The complete architecture has been made using the Xilinx software and the implementation has been implemented on the target device: xc5vlx110t-3ff1136.

Load all the verilog codes that you download in a single project on Xilinx.

1. CU.V is the main black box or you can say your basic computer that includes all the hardware and wirings inside it.

2. MEM.V is the ROM memory being used for this example. It has a capacity to store 256words of 16 bits each. I could have used 2 separate memories for instructions and data but being stuck with making a ‘basic’ example I left out the same. You are, although, eligible to do the same ;)

3. SIGNALS.V is the signal generator module that provides all the required timing signals for the computer to work with. It’s basically the T0, T1, T2… timing signals which are used to schedule the fetch and execute instructions through the control block.

4. REGISTER.V is a basic module describing the registers of the architecture. Anyone with hands on Verilog can hold it with ease.

5. ALU.V is the block that describes the Arithmetic Logic Unit of the system. This module takes the signal from the control block and performs all the operations related with the Accumulator (AC) and the carry flip-flop (E).

6. FF.V implements the flip-flop model. I have only used the E flip-flop. Anyone who is more excited can use this module to extend the complete design by including the parity, sign and other flip-flops to this basic architectue design.

7. OPCODE.V is used to reduce the complexity involved with decoding the Instruction register’s (IR) higher bits. This decoder is used to decode the 12,13 and 14 bits of the IR code.

8. CTRL.V is the heart of the design. Yeah! you guessed right, this module describes all the timing sequences associated with computer.