Cherry pick ben's docs changes

README.md

@@ -47,8 +47,10 @@ opam exec -- dune build
 opam exec -- dune runtest
 ```
 
-Now please continue to the relevant section listed [above](#zprize-submissions)
-to build the top level designs from source.
+Now please continue to the relevant to build the top level designs from source.
+
+- [MSM](zprize/msm_pippenger/README.md)
+- [NTT](zprize/ntt/)
 
 # Contributing
 

zprize/msm_pippenger/README.md

@@ -143,7 +143,7 @@ still being able to successfully route in Vivado.
 Instructions are given below for building from source. A prerequisite is that
 OCaml has been setup (outlined in the main [README.md](../../README.md)).
 
-It is important you use the AMI version 1.10.5 and Vivado version 2020.2 to
+It is important you use the [FPGA Developer AMI (Amazon Linux 2)](https://aws.amazon.com/marketplace/pp/prodview-iehshpgi7hcjg) version 1.10.5 and Vivado version 2020.2 to
 acheive the same results. The rtl_checksum expected of the Verilog when
 generated from the Hardcaml source is 1929f78e1e4bafd9cf88d507a3afa055.
 
@@ -188,8 +188,7 @@ more points.
 ## Building an FPGA image for AWS
 
 You need to clone the [aws-fpga repo](https://github.com/aws/aws-fpga/), as well
-as run on an AWS box with the [FPGA Developer
-AMI](https://aws.amazon.com/marketplace/pp/prodview-gimv3gqbpe57k) installed.
+as run on an AWS box with the [FPGA Developer AMI (Amazon Linux 2)](https://aws.amazon.com/marketplace/pp/prodview-iehshpgi7hcjg) installed.
 
 ```
 source ~/aws-fpga/vitis_setup.sh