WIP: SPI bus driver

[Tejasgarg]

• fixes: Develop basic SPI bus #126

This is a work in progress.

Currently, I have implemented the basic low-level driver for SPI bus, that implements two SPI buses (SPI1 and SPI2)

I will continue working on this to implement the complete working of the SPI bus module

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[bessman]

Get it working without DMA first.

[bessman]

GPDMA1 channels 6 and 7 are used by ADC. 2,3,4,5 are free.

[bessman]

Scratch that, they're all in use by UART. Skip DMA for now, we may need to use DMA2 for this.

[bessman]

Get it working without interrupts first.

[bessman]

SPI has no clock source. It must be enabled in system_clock_config in platform.c. E.g.

--- a/src/platform/h563xx/platform.c
+++ b/src/platform/h563xx/platform.c
@@ -137,8 +137,9 @@ static void system_clock_config(void)

     /* Configure peripheral clocks - Set ADC clock source to PLL2R (75 MHz) */
     RCC_PeriphCLKInitTypeDef periph_clk_init = { 0 };
-    periph_clk_init.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC;
+    periph_clk_init.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_SPI1;
     periph_clk_init.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_PLL2R;
+    periph_clk_init.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL2P;

     // Configure PLL2 structure to match our desired configuration
     // This is required because HAL_RCCEx_PeriphCLKConfig calls
@@ -147,15 +148,17 @@ static void system_clock_config(void)
     periph_clk_init.PLL2.PLL2M = 2; // 8 MHz / 2 = 4 MHz
     // NOLINTNEXTLINE: readability-magic-numbers
     periph_clk_init.PLL2.PLL2N = 75; // 4 MHz * 75 = 300 MHz VCO
-    periph_clk_init.PLL2.PLL2P = 2; // 300 MHz / 2 = 150 MHz
+    periph_clk_init.PLL2.PLL2P = 3; // 300 MHz / 3 = 100 MHz (for SPI1)
     periph_clk_init.PLL2.PLL2Q = 2; // 300 MHz / 2 = 150 MHz
     periph_clk_init.PLL2.PLL2R = 4; // 300 MHz / 4 = 75 MHz (for ADC)
     periph_clk_init.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_1; // 2-4 MHz input range
     periph_clk_init.PLL2.PLL2VCOSEL =
         RCC_PLL2_VCORANGE_MEDIUM; // 150-420 MHz VCO
     periph_clk_init.PLL2.PLL2FRACN = 0;
+    // Enable PLL2 clock outputs
     periph_clk_init.PLL2.PLL2ClockOut =
-        RCC_PLL2_DIVR; // Enable PLL2R output for ADC
+        RCC_PLL2_DIVR | // Enable PLL2R output for ADC
+        RCC_PLL2_DIVP; // Enable PLL2P output for SPI1

     if (HAL_RCCEx_PeriphCLKConfig(&periph_clk_init) != HAL_OK) {
         /* ADC clock configuration failed */