Name		Name	Last commit message	Last commit date
Latest commit History 114 Commits
FixedPointAdder		FixedPointAdder
average_filter		average_filter
boxcar_filter		boxcar_filter
delayw		delayw
hsFIR/test_rtl		hsFIR/test_rtl
nco		nco
simpleFixedPointSignedLongDivision		simpleFixedPointSignedLongDivision
simpleFixedPointUnsignedLongDivision		simpleFixedPointUnsignedLongDivision
simpleLongDivision		simpleLongDivision
sintable		sintable
sqrtFixedPoint		sqrtFixedPoint
wbpwmaudio		wbpwmaudio
.gitattributes		.gitattributes
.gitignore		.gitignore
CHANGELOG.md		CHANGELOG.md
README.md		README.md
TODO.md		TODO.md

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DSP FPGA filters in Verilog

average_filter

boxcar_filter

delayw - Configurable Delay

hsFIR - High Speed FIR Filter

nco - Numerically Controlled Oscillator

sintable - Simplest Sin LUT

wbpwmaudio - Bit-Reversed PWM Audio DAC

simpleLongDivision

simpleFixedPointUnsignedLongDivision

simpleFixedPointSignedLongDivision

sqrtFixedPoint

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