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gerekongerekon
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esp32: Fixes registers retrieval during stepping
Also fixes DSR reading for APP core in xtensa_poll
1 parent 62b6f53 commit fb49eea

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2 files changed

+28
-21
lines changed

2 files changed

+28
-21
lines changed

‎src/target/esp108.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -327,7 +327,7 @@ int esp108_write_dirty_registers(struct target *target)
327327
regval=esp108_reg_get(&reg_list[realadr]);
328328
LOG_DEBUG("%s: Writing back reg %s value %08X", target->cmd_name, esp108_regs[realadr].name, regval);
329329
esp108_queue_nexus_reg_write(target, NARADR_DDR, regval);
330-
esp108_queue_exec_ins(target, XT_INS_RSR(XT_SR_DDR, esp108_regs[XT_REG_IDX_AR0+i+j].reg_num));
330+
esp108_queue_exec_ins(target, XT_INS_RSR(XT_SR_DDR, esp108_regs[XT_REG_IDX_AR0+i].reg_num));
331331
reg_list[realadr].dirty=0;
332332
}
333333
}

‎src/target/esp32.c

Lines changed: 27 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -114,7 +114,7 @@ static void esp32_mark_register_dirty(struct reg *reg_list, int regidx)
114114
reg_list[regidx].dirty=1;
115115
}
116116

117-
static int esp32_fetch_all_regs(struct target *target)
117+
static int esp32_fetch_all_regs(struct target *target, uint8_t cpu_mask)
118118
{
119119
int i, j;
120120
int cpenable;
@@ -139,6 +139,9 @@ static int esp32_fetch_all_regs(struct target *target)
139139
// Read registers from both cores
140140
for (size_t c = 0; c < ESP32_CPU_COUNT; c++)
141141
{
142+
if ((cpu_mask & (1 << c)) == 0) {
143+
continue;
144+
}
142145
//Start out with A0-A63; we can reach those immediately. Grab them per 16 registers.
143146
for (j = 0; j < 64; j += 16) {
144147
//Grab the 16 registers we can see
@@ -160,7 +163,10 @@ static int esp32_fetch_all_regs(struct target *target)
160163

161164

162165
res=jtag_execute_queue();
163-
if (res!=ERROR_OK) return res;
166+
if (res!=ERROR_OK) {
167+
LOG_ERROR("Failed to read ARs (%d)!\n", res);
168+
return res;
169+
}
164170

165171
esp32_checkdsr(esp32->esp32_targets[c]);
166172
cpenable = intfromchars(regvals[c][XT_REG_IDX_CPENABLE]);
@@ -169,7 +175,7 @@ static int esp32_fetch_all_regs(struct target *target)
169175
//We're now free to use any of A0-A15 as scratch registers
170176
//Grab the SFRs and user registers first. We use A3 as a scratch register.
171177
for (i = 0; i < XT_NUM_REGS; i++) {
172-
if (regReadable(esp32_regs[i].flags, cpenable) && (esp32_regs[i].type == XT_REG_SPECIAL || esp32_regs[i].type == XT_REG_USER)) {
178+
if (regReadable(esp32_regs[i].flags, cpenable) && (esp32_regs[i].type == XT_REG_SPECIAL || esp32_regs[i].type == XT_REG_USER || esp32_regs[i].type == XT_REG_FR)) {
173179
if (esp32_regs[i].type == XT_REG_USER) {
174180
esp108_queue_exec_ins(esp32->esp32_targets[c], XT_INS_RUR(esp32_regs[i].reg_num, XT_REG_A3));
175181
}
@@ -187,12 +193,15 @@ static int esp32_fetch_all_regs(struct target *target)
187193

188194
//Ok, send the whole mess to the CPU.
189195
res=jtag_execute_queue();
190-
if (res!=ERROR_OK) return res;
196+
if (res!=ERROR_OK) {
197+
LOG_ERROR("Failed to fetch AR regs!\n");
198+
return res;
199+
}
191200

192201
esp32_checkdsr(esp32->esp32_targets[c]);
193202
//DSR checking: follows order in which registers are requested.
194203
for (i = 0; i < XT_NUM_REGS; i++) {
195-
if (regReadable(esp32_regs[i].flags, cpenable) && (esp32_regs[i].type == XT_REG_SPECIAL || esp32_regs[i].type == XT_REG_USER)) {
204+
if (regReadable(esp32_regs[i].flags, cpenable) && (esp32_regs[i].type == XT_REG_SPECIAL || esp32_regs[i].type == XT_REG_USER || esp32_regs[i].type == XT_REG_FR)) {
196205
if (intfromchars(dsrs[c][i])&OCDDSR_EXECEXCEPTION) {
197206
LOG_ERROR("Exception reading %s!\n", esp32_regs[i].name);
198207
return ERROR_FAIL;
@@ -233,7 +242,6 @@ static int esp32_fetch_all_regs(struct target *target)
233242
struct reg *cpu_reg_list = esp32->core_caches[c]->reg_list;
234243
esp32_mark_register_dirty(cpu_reg_list, XT_REG_IDX_A3);
235244
}
236-
esp32_checkdsr(esp32->esp32_targets[0]);
237245
return ERROR_OK;
238246
}
239247

@@ -306,7 +314,7 @@ static int esp32_write_dirty_registers(struct target *target, struct reg *reg_li
306314
regval=esp108_reg_get(&reg_list[realadr]);
307315
LOG_DEBUG("%s: Writing back reg %s value %08X, num =%i", target->cmd_name, esp32_regs[realadr].name, regval, esp32_regs[realadr].reg_num);
308316
esp108_queue_nexus_reg_write(target, NARADR_DDR, regval);
309-
esp108_queue_exec_ins(target, XT_INS_RSR(XT_SR_DDR, esp32_regs[XT_REG_IDX_AR0+i+j].reg_num));
317+
esp108_queue_exec_ins(target, XT_INS_RSR(XT_SR_DDR, esp32_regs[XT_REG_IDX_AR0+i].reg_num));
310318
reg_list[realadr].dirty=0;
311319
}
312320
}
@@ -962,7 +970,6 @@ static int xtensa_step(struct target *target,
962970
static const uint32_t icount_val = -2; /* ICOUNT value to load for 1 step */
963971
uint32_t icountlvl;
964972
uint32_t oldps, newps, oldpc;
965-
int tries=10;
966973

967974
LOG_DEBUG("%s: %s(current=%d, address=0x%04x, handle_breakpoints=%i)", target->cmd_name, __func__, current, address, handle_breakpoints);
968975

@@ -1011,7 +1018,6 @@ static int xtensa_step(struct target *target,
10111018

10121019

10131020
do {
1014-
// We have equival amount of BP for each cpu
10151021
{
10161022
struct reg *cpu_reg_list = esp32->core_caches[esp32->active_cpu]->reg_list;
10171023
esp108_reg_set(&cpu_reg_list[XT_REG_IDX_ICOUNTLEVEL], icountlvl);
@@ -1047,22 +1053,23 @@ static int xtensa_step(struct target *target,
10471053
if(!(intfromchars(dsr)&OCDDSR_STOPPED)) {
10481054
LOG_ERROR("%s: %s: Timed out waiting for target to finish stepping. dsr=0x%08x", target->cmd_name, __func__, intfromchars(dsr));
10491055
return ERROR_TARGET_TIMEOUT;
1050-
} else
1051-
{
1052-
target->state = TARGET_HALTED;
1053-
esp32_fetch_all_regs(target);
10541056
}
1055-
} while (esp108_reg_get(&reg_list[XT_REG_IDX_PC])==oldpc && --tries);
1056-
LOG_DEBUG("Stepped from %X to %X", oldpc, esp108_reg_get(&reg_list[XT_REG_IDX_PC]));
1057+
esp32_fetch_all_regs(target, 1 << esp32->active_cpu);
1058+
} while (0);
10571059

1058-
if (!tries) {
1060+
uint32_t cur_pc = esp108_reg_get(&reg_list[XT_REG_IDX_PC]);
1061+
if (oldpc == cur_pc) {
10591062
LOG_WARNING("%s: %s: Stepping doesn't seem to change PC! dsr=0x%08x", target->cmd_name, __func__, intfromchars(dsr));
10601063
}
1061-
1064+
else {
1065+
LOG_DEBUG("Stepped from %X to %X", oldpc, cur_pc);
1066+
}
10621067
// This operation required to clear state
10631068
for (size_t cp = 0; cp < ESP32_CPU_COUNT; cp++)
10641069
{
1065-
if (cp != esp32->active_cpu) xtensa_read_dsr(esp32->esp32_targets[cp]);
1070+
if (cp != esp32->active_cpu) {
1071+
xtensa_read_dsr(esp32->esp32_targets[cp]);
1072+
}
10661073
}
10671074

10681075
if (cause&DEBUGCAUSE_DB) {
@@ -1359,7 +1366,7 @@ static int xtensa_poll(struct target *target)
13591366
}
13601367

13611368
unsigned int dsr0 = intfromchars(dsr[0]);
1362-
unsigned int dsr1 = intfromchars(dsr[0]);
1369+
unsigned int dsr1 = intfromchars(dsr[1]);
13631370
unsigned int common_reason = dsr0 | dsr1; // We should know if even one of CPU was stopped
13641371

13651372
unsigned int common_pwrstath = pwrstath[0] | pwrstath[1];
@@ -1369,7 +1376,7 @@ static int xtensa_poll(struct target *target)
13691376
LOG_DEBUG("Stopped: CPU0: %d CPU1: %d", (dsr0 & OCDDSR_STOPPED) ? 1 : 0, (dsr1 & OCDDSR_STOPPED) ? 1 : 0);
13701377
xtensa_halt(target);
13711378
target->state = TARGET_HALTED;
1372-
esp32_fetch_all_regs(target);
1379+
esp32_fetch_all_regs(target, 0x3);
13731380
//Examine why the target was halted
13741381
target->debug_reason = DBG_REASON_DBGRQ;
13751382
for (size_t i = 0; i < ESP32_CPU_COUNT; i++)

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