Clean up interrupt registers names for TIMGx

common_patches/tim_collect.yaml

@@ -1,4 +1,3 @@
-
 _cluster:
   T%s:
     dimIncrement: 0x24
@@ -21,16 +20,16 @@ _cluster:
     T?LOAD:
       name: LOAD
 
-INT_ENA_TIMERS:
+INT_ENA:
   _array:
     T?: {}
-INT_RAW_TIMERS:
+INT_RAW:
   _array:
     T?: {}
-INT_ST_TIMERS:
+INT_ST:
   _array:
     T?: {}
-INT_CLR_TIMERS:
+INT_CLR:
   _array:
     T?: {}
 

common_patches/tim_int_strip.yaml

@@ -1,10 +1,12 @@
-INT_RAW_TIMERS:
+_strip_end: _TIMERS
+
+INT_RAW:
   _strip_end: _INT_RAW
-INT_ST_TIMERS:
+INT_ST:
   _strip_end: _INT_ST
-INT_ENA_TIMERS:
+INT_ENA:
   _strip_end: _INT_ENA
-INT_CLR_TIMERS:
+INT_CLR:
   _strip_end: _INT_CLR
   _modify:
     "*":

esp32/src/timg0.rs

@@ -23,10 +23,10 @@ pub struct RegisterBlock {
     lactloadlo: LACTLOADLO,
     lactloadhi: LACTLOADHI,
     lactload: LACTLOAD,
-    int_ena_timers: INT_ENA_TIMERS,
-    int_raw_timers: INT_RAW_TIMERS,
-    int_st_timers: INT_ST_TIMERS,
-    int_clr_timers: INT_CLR_TIMERS,
+    int_ena: INT_ENA,
+    int_raw: INT_RAW,
+    int_st: INT_ST,
+    int_clr: INT_CLR,
     _reserved25: [u8; 0x50],
     ntimers_date: NTIMERS_DATE,
     timgclk: TIMGCLK,
@@ -145,23 +145,23 @@ impl RegisterBlock {
     }
     #[doc = "0x98 - "]
     #[inline(always)]
-    pub const fn int_ena_timers(&self) -> &INT_ENA_TIMERS {
-        &self.int_ena_timers
+    pub const fn int_ena(&self) -> &INT_ENA {
+        &self.int_ena
     }
     #[doc = "0x9c - "]
     #[inline(always)]
-    pub const fn int_raw_timers(&self) -> &INT_RAW_TIMERS {
-        &self.int_raw_timers
+    pub const fn int_raw(&self) -> &INT_RAW {
+        &self.int_raw
     }
     #[doc = "0xa0 - "]
     #[inline(always)]
-    pub const fn int_st_timers(&self) -> &INT_ST_TIMERS {
-        &self.int_st_timers
+    pub const fn int_st(&self) -> &INT_ST {
+        &self.int_st
     }
     #[doc = "0xa4 - "]
     #[inline(always)]
-    pub const fn int_clr_timers(&self) -> &INT_CLR_TIMERS {
-        &self.int_clr_timers
+    pub const fn int_clr(&self) -> &INT_CLR {
+        &self.int_clr
     }
     #[doc = "0xf8 - "]
     #[inline(always)]
@@ -259,22 +259,22 @@ pub mod lactloadhi;
 pub type LACTLOAD = crate::Reg<lactload::LACTLOAD_SPEC>;
 #[doc = ""]
 pub mod lactload;
-#[doc = "INT_ENA_TIMERS (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena_timers::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena_timers::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena_timers`] module"]
-pub type INT_ENA_TIMERS = crate::Reg<int_ena_timers::INT_ENA_TIMERS_SPEC>;
+#[doc = "INT_ENA (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"]
+pub type INT_ENA = crate::Reg<int_ena::INT_ENA_SPEC>;
 #[doc = ""]
-pub mod int_ena_timers;
-#[doc = "INT_RAW_TIMERS (r) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw_timers::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw_timers`] module"]
-pub type INT_RAW_TIMERS = crate::Reg<int_raw_timers::INT_RAW_TIMERS_SPEC>;
+pub mod int_ena;
+#[doc = "INT_RAW (r) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"]
+pub type INT_RAW = crate::Reg<int_raw::INT_RAW_SPEC>;
 #[doc = ""]
-pub mod int_raw_timers;
-#[doc = "INT_ST_TIMERS (r) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`int_st_timers::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st_timers`] module"]
-pub type INT_ST_TIMERS = crate::Reg<int_st_timers::INT_ST_TIMERS_SPEC>;
+pub mod int_raw;
+#[doc = "INT_ST (r) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"]
+pub type INT_ST = crate::Reg<int_st::INT_ST_SPEC>;
 #[doc = ""]
-pub mod int_st_timers;
-#[doc = "INT_CLR_TIMERS (w) register accessor: \n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr_timers::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr_timers`] module"]
-pub type INT_CLR_TIMERS = crate::Reg<int_clr_timers::INT_CLR_TIMERS_SPEC>;
+pub mod int_st;
+#[doc = "INT_CLR (w) register accessor: \n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
+pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
 #[doc = ""]
-pub mod int_clr_timers;
+pub mod int_clr;
 #[doc = "NTIMERS_DATE (rw) register accessor: \n\nYou can [`read`](crate::Reg::read) this register and get [`ntimers_date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ntimers_date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ntimers_date`] module"]
 pub type NTIMERS_DATE = crate::Reg<ntimers_date::NTIMERS_DATE_SPEC>;
 #[doc = ""]

esp32/src/timg0/int_clr_timers.rs → esp32/src/timg0/int_clr.rs

@@ -1,13 +1,13 @@
-#[doc = "Register `INT_CLR_TIMERS` writer"]
-pub type W = crate::W<INT_CLR_TIMERS_SPEC>;
+#[doc = "Register `INT_CLR` writer"]
+pub type W = crate::W<INT_CLR_SPEC>;
 #[doc = "Field `T(0-1)` writer - interrupt when timer%s alarm"]
 pub type T_W<'a, REG> = crate::BitWriter1C<'a, REG>;
 #[doc = "Field `WDT` writer - Interrupt when an interrupt stage timeout"]
 pub type WDT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
 #[doc = "Field `LACT` writer - "]
 pub type LACT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
 #[cfg(feature = "impl-register-debug")]
-impl core::fmt::Debug for crate::generic::Reg<INT_CLR_TIMERS_SPEC> {
+impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
     fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
         write!(f, "(not readable)")
     }
@@ -18,48 +18,48 @@ impl W {
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `T0` field.</div>"]
     #[inline(always)]
     #[must_use]
-    pub fn t(&mut self, n: u8) -> T_W<INT_CLR_TIMERS_SPEC> {
+    pub fn t(&mut self, n: u8) -> T_W<INT_CLR_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
         T_W::new(self, n)
     }
     #[doc = "Bit 0 - interrupt when timer0 alarm"]
     #[inline(always)]
     #[must_use]
-    pub fn t0(&mut self) -> T_W<INT_CLR_TIMERS_SPEC> {
+    pub fn t0(&mut self) -> T_W<INT_CLR_SPEC> {
         T_W::new(self, 0)
     }
     #[doc = "Bit 1 - interrupt when timer1 alarm"]
     #[inline(always)]
     #[must_use]
-    pub fn t1(&mut self) -> T_W<INT_CLR_TIMERS_SPEC> {
+    pub fn t1(&mut self) -> T_W<INT_CLR_SPEC> {
         T_W::new(self, 1)
     }
     #[doc = "Bit 2 - Interrupt when an interrupt stage timeout"]
     #[inline(always)]
     #[must_use]
-    pub fn wdt(&mut self) -> WDT_W<INT_CLR_TIMERS_SPEC> {
+    pub fn wdt(&mut self) -> WDT_W<INT_CLR_SPEC> {
         WDT_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
     #[must_use]
-    pub fn lact(&mut self) -> LACT_W<INT_CLR_TIMERS_SPEC> {
+    pub fn lact(&mut self) -> LACT_W<INT_CLR_SPEC> {
         LACT_W::new(self, 3)
     }
 }
-#[doc = "\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr_timers::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
-pub struct INT_CLR_TIMERS_SPEC;
-impl crate::RegisterSpec for INT_CLR_TIMERS_SPEC {
+#[doc = "\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_CLR_SPEC;
+impl crate::RegisterSpec for INT_CLR_SPEC {
     type Ux = u32;
 }
-#[doc = "`write(|w| ..)` method takes [`int_clr_timers::W`](W) writer structure"]
-impl crate::Writable for INT_CLR_TIMERS_SPEC {
+#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
+impl crate::Writable for INT_CLR_SPEC {
     type Safety = crate::Unsafe;
     const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
     const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0d;
 }
-#[doc = "`reset()` method sets INT_CLR_TIMERS to value 0"]
-impl crate::Resettable for INT_CLR_TIMERS_SPEC {
+#[doc = "`reset()` method sets INT_CLR to value 0"]
+impl crate::Resettable for INT_CLR_SPEC {
     const RESET_VALUE: u32 = 0;
 }

esp32/src/timg0/int_ena_timers.rs → esp32/src/timg0/int_ena.rs

@@ -1,7 +1,7 @@
-#[doc = "Register `INT_ENA_TIMERS` reader"]
-pub type R = crate::R<INT_ENA_TIMERS_SPEC>;
-#[doc = "Register `INT_ENA_TIMERS` writer"]
-pub type W = crate::W<INT_ENA_TIMERS_SPEC>;
+#[doc = "Register `INT_ENA` reader"]
+pub type R = crate::R<INT_ENA_SPEC>;
+#[doc = "Register `INT_ENA` writer"]
+pub type W = crate::W<INT_ENA_SPEC>;
 #[doc = "Field `T(0-1)` reader - interrupt when timer%s alarm"]
 pub type T_R = crate::BitReader;
 #[doc = "Field `T(0-1)` writer - interrupt when timer%s alarm"]
@@ -54,7 +54,7 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("INT_ENA_TIMERS")
+        f.debug_struct("INT_ENA")
             .field("t0", &self.t0())
             .field("t1", &self.t1())
             .field("wdt", &self.wdt())
@@ -68,50 +68,50 @@ impl W {
     #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `T0` field.</div>"]
     #[inline(always)]
     #[must_use]
-    pub fn t(&mut self, n: u8) -> T_W<INT_ENA_TIMERS_SPEC> {
+    pub fn t(&mut self, n: u8) -> T_W<INT_ENA_SPEC> {
         #[allow(clippy::no_effect)]
         [(); 2][n as usize];
         T_W::new(self, n)
     }
     #[doc = "Bit 0 - interrupt when timer0 alarm"]
     #[inline(always)]
     #[must_use]
-    pub fn t0(&mut self) -> T_W<INT_ENA_TIMERS_SPEC> {
+    pub fn t0(&mut self) -> T_W<INT_ENA_SPEC> {
         T_W::new(self, 0)
     }
     #[doc = "Bit 1 - interrupt when timer1 alarm"]
     #[inline(always)]
     #[must_use]
-    pub fn t1(&mut self) -> T_W<INT_ENA_TIMERS_SPEC> {
+    pub fn t1(&mut self) -> T_W<INT_ENA_SPEC> {
         T_W::new(self, 1)
     }
     #[doc = "Bit 2 - Interrupt when an interrupt stage timeout"]
     #[inline(always)]
     #[must_use]
-    pub fn wdt(&mut self) -> WDT_W<INT_ENA_TIMERS_SPEC> {
+    pub fn wdt(&mut self) -> WDT_W<INT_ENA_SPEC> {
         WDT_W::new(self, 2)
     }
     #[doc = "Bit 3"]
     #[inline(always)]
     #[must_use]
-    pub fn lact(&mut self) -> LACT_W<INT_ENA_TIMERS_SPEC> {
+    pub fn lact(&mut self) -> LACT_W<INT_ENA_SPEC> {
         LACT_W::new(self, 3)
     }
 }
-#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena_timers::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena_timers::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
-pub struct INT_ENA_TIMERS_SPEC;
-impl crate::RegisterSpec for INT_ENA_TIMERS_SPEC {
+#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_ENA_SPEC;
+impl crate::RegisterSpec for INT_ENA_SPEC {
     type Ux = u32;
 }
-#[doc = "`read()` method returns [`int_ena_timers::R`](R) reader structure"]
-impl crate::Readable for INT_ENA_TIMERS_SPEC {}
-#[doc = "`write(|w| ..)` method takes [`int_ena_timers::W`](W) writer structure"]
-impl crate::Writable for INT_ENA_TIMERS_SPEC {
+#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
+impl crate::Readable for INT_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
+impl crate::Writable for INT_ENA_SPEC {
     type Safety = crate::Unsafe;
     const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
     const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
-#[doc = "`reset()` method sets INT_ENA_TIMERS to value 0"]
-impl crate::Resettable for INT_ENA_TIMERS_SPEC {
+#[doc = "`reset()` method sets INT_ENA to value 0"]
+impl crate::Resettable for INT_ENA_SPEC {
     const RESET_VALUE: u32 = 0;
 }

esp32/src/timg0/int_st_timers.rs → esp32/src/timg0/int_raw.rs

@@ -1,5 +1,5 @@
-#[doc = "Register `INT_ST_TIMERS` reader"]
-pub type R = crate::R<INT_ST_TIMERS_SPEC>;
+#[doc = "Register `INT_RAW` reader"]
+pub type R = crate::R<INT_RAW_SPEC>;
 #[doc = "Field `T(0-1)` reader - interrupt when timer%s alarm"]
 pub type T_R = crate::BitReader;
 #[doc = "Field `WDT` reader - Interrupt when an interrupt stage timeout"]
@@ -46,22 +46,22 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("INT_ST_TIMERS")
+        f.debug_struct("INT_RAW")
             .field("t0", &self.t0())
             .field("t1", &self.t1())
             .field("wdt", &self.wdt())
             .field("lact", &self.lact())
             .finish()
     }
 }
-#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st_timers::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
-pub struct INT_ST_TIMERS_SPEC;
-impl crate::RegisterSpec for INT_ST_TIMERS_SPEC {
+#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_RAW_SPEC;
+impl crate::RegisterSpec for INT_RAW_SPEC {
     type Ux = u32;
 }
-#[doc = "`read()` method returns [`int_st_timers::R`](R) reader structure"]
-impl crate::Readable for INT_ST_TIMERS_SPEC {}
-#[doc = "`reset()` method sets INT_ST_TIMERS to value 0"]
-impl crate::Resettable for INT_ST_TIMERS_SPEC {
+#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
+impl crate::Readable for INT_RAW_SPEC {}
+#[doc = "`reset()` method sets INT_RAW to value 0"]
+impl crate::Resettable for INT_RAW_SPEC {
     const RESET_VALUE: u32 = 0;
 }

esp32/src/timg0/int_raw_timers.rs → esp32/src/timg0/int_st.rs

@@ -1,5 +1,5 @@
-#[doc = "Register `INT_RAW_TIMERS` reader"]
-pub type R = crate::R<INT_RAW_TIMERS_SPEC>;
+#[doc = "Register `INT_ST` reader"]
+pub type R = crate::R<INT_ST_SPEC>;
 #[doc = "Field `T(0-1)` reader - interrupt when timer%s alarm"]
 pub type T_R = crate::BitReader;
 #[doc = "Field `WDT` reader - Interrupt when an interrupt stage timeout"]
@@ -46,22 +46,22 @@ impl R {
 #[cfg(feature = "impl-register-debug")]
 impl core::fmt::Debug for R {
     fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
-        f.debug_struct("INT_RAW_TIMERS")
+        f.debug_struct("INT_ST")
             .field("t0", &self.t0())
             .field("t1", &self.t1())
             .field("wdt", &self.wdt())
             .field("lact", &self.lact())
             .finish()
     }
 }
-#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw_timers::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
-pub struct INT_RAW_TIMERS_SPEC;
-impl crate::RegisterSpec for INT_RAW_TIMERS_SPEC {
+#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct INT_ST_SPEC;
+impl crate::RegisterSpec for INT_ST_SPEC {
     type Ux = u32;
 }
-#[doc = "`read()` method returns [`int_raw_timers::R`](R) reader structure"]
-impl crate::Readable for INT_RAW_TIMERS_SPEC {}
-#[doc = "`reset()` method sets INT_RAW_TIMERS to value 0"]
-impl crate::Resettable for INT_RAW_TIMERS_SPEC {
+#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
+impl crate::Readable for INT_ST_SPEC {}
+#[doc = "`reset()` method sets INT_ST to value 0"]
+impl crate::Resettable for INT_ST_SPEC {
     const RESET_VALUE: u32 = 0;
 }