Patch the HP_SYS peripheral (#184)

esp32p4/src/hp_sys/ahb2axi_bresp_err_int_clr.rs

@@ -0,0 +1,44 @@
+#[doc = "Register `AHB2AXI_BRESP_ERR_INT_CLR` writer"]
+pub type W = crate::W<AHB2AXI_BRESP_ERR_INT_CLR_SPEC>;
+#[doc = "Field `CPU_ICM_H2X_BRESP_ERR_INT_CLR` writer - Write 1 to clear cpu_icm_h2x_bresp_err int"]
+pub type CPU_ICM_H2X_BRESP_ERR_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<AHB2AXI_BRESP_ERR_INT_CLR_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {
+    #[doc = "Bit 31 - Write 1 to clear cpu_icm_h2x_bresp_err int"]
+    #[inline(always)]
+    #[must_use]
+    pub fn cpu_icm_h2x_bresp_err_int_clr(
+        &mut self,
+    ) -> CPU_ICM_H2X_BRESP_ERR_INT_CLR_W<AHB2AXI_BRESP_ERR_INT_CLR_SPEC> {
+        CPU_ICM_H2X_BRESP_ERR_INT_CLR_W::new(self, 31)
+    }
+    #[doc = r" Writes raw bits to the register."]
+    #[doc = r""]
+    #[doc = r" # Safety"]
+    #[doc = r""]
+    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
+#[doc = "need_des\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb2axi_bresp_err_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct AHB2AXI_BRESP_ERR_INT_CLR_SPEC;
+impl crate::RegisterSpec for AHB2AXI_BRESP_ERR_INT_CLR_SPEC {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`ahb2axi_bresp_err_int_clr::W`](W) writer structure"]
+impl crate::Writable for AHB2AXI_BRESP_ERR_INT_CLR_SPEC {
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets AHB2AXI_BRESP_ERR_INT_CLR to value 0"]
+impl crate::Resettable for AHB2AXI_BRESP_ERR_INT_CLR_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

esp32p4/src/hp_sys/ahb2axi_bresp_err_int_ena.rs

@@ -0,0 +1,68 @@
+#[doc = "Register `AHB2AXI_BRESP_ERR_INT_ENA` reader"]
+pub type R = crate::R<AHB2AXI_BRESP_ERR_INT_ENA_SPEC>;
+#[doc = "Register `AHB2AXI_BRESP_ERR_INT_ENA` writer"]
+pub type W = crate::W<AHB2AXI_BRESP_ERR_INT_ENA_SPEC>;
+#[doc = "Field `CPU_ICM_H2X_BRESP_ERR_INT_ENA` reader - Write 1 to enable cpu_icm_h2x_bresp_err int"]
+pub type CPU_ICM_H2X_BRESP_ERR_INT_ENA_R = crate::BitReader;
+#[doc = "Field `CPU_ICM_H2X_BRESP_ERR_INT_ENA` writer - Write 1 to enable cpu_icm_h2x_bresp_err int"]
+pub type CPU_ICM_H2X_BRESP_ERR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 31 - Write 1 to enable cpu_icm_h2x_bresp_err int"]
+    #[inline(always)]
+    pub fn cpu_icm_h2x_bresp_err_int_ena(&self) -> CPU_ICM_H2X_BRESP_ERR_INT_ENA_R {
+        CPU_ICM_H2X_BRESP_ERR_INT_ENA_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("AHB2AXI_BRESP_ERR_INT_ENA")
+            .field(
+                "cpu_icm_h2x_bresp_err_int_ena",
+                &format_args!("{}", self.cpu_icm_h2x_bresp_err_int_ena().bit()),
+            )
+            .finish()
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<AHB2AXI_BRESP_ERR_INT_ENA_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
+impl W {
+    #[doc = "Bit 31 - Write 1 to enable cpu_icm_h2x_bresp_err int"]
+    #[inline(always)]
+    #[must_use]
+    pub fn cpu_icm_h2x_bresp_err_int_ena(
+        &mut self,
+    ) -> CPU_ICM_H2X_BRESP_ERR_INT_ENA_W<AHB2AXI_BRESP_ERR_INT_ENA_SPEC> {
+        CPU_ICM_H2X_BRESP_ERR_INT_ENA_W::new(self, 31)
+    }
+    #[doc = r" Writes raw bits to the register."]
+    #[doc = r""]
+    #[doc = r" # Safety"]
+    #[doc = r""]
+    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
+#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb2axi_bresp_err_int_ena::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb2axi_bresp_err_int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct AHB2AXI_BRESP_ERR_INT_ENA_SPEC;
+impl crate::RegisterSpec for AHB2AXI_BRESP_ERR_INT_ENA_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ahb2axi_bresp_err_int_ena::R`](R) reader structure"]
+impl crate::Readable for AHB2AXI_BRESP_ERR_INT_ENA_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ahb2axi_bresp_err_int_ena::W`](W) writer structure"]
+impl crate::Writable for AHB2AXI_BRESP_ERR_INT_ENA_SPEC {
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets AHB2AXI_BRESP_ERR_INT_ENA to value 0"]
+impl crate::Resettable for AHB2AXI_BRESP_ERR_INT_ENA_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

esp32p4/src/hp_sys/ahb2axi_bresp_err_int_raw.rs

@@ -0,0 +1,68 @@
+#[doc = "Register `AHB2AXI_BRESP_ERR_INT_RAW` reader"]
+pub type R = crate::R<AHB2AXI_BRESP_ERR_INT_RAW_SPEC>;
+#[doc = "Register `AHB2AXI_BRESP_ERR_INT_RAW` writer"]
+pub type W = crate::W<AHB2AXI_BRESP_ERR_INT_RAW_SPEC>;
+#[doc = "Field `CPU_ICM_H2X_BRESP_ERR_INT_RAW` reader - the raw interrupt status of bresp error, triggered when if bresp err occurs in post write mode in ahb2axi."]
+pub type CPU_ICM_H2X_BRESP_ERR_INT_RAW_R = crate::BitReader;
+#[doc = "Field `CPU_ICM_H2X_BRESP_ERR_INT_RAW` writer - the raw interrupt status of bresp error, triggered when if bresp err occurs in post write mode in ahb2axi."]
+pub type CPU_ICM_H2X_BRESP_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - the raw interrupt status of bresp error, triggered when if bresp err occurs in post write mode in ahb2axi."]
+    #[inline(always)]
+    pub fn cpu_icm_h2x_bresp_err_int_raw(&self) -> CPU_ICM_H2X_BRESP_ERR_INT_RAW_R {
+        CPU_ICM_H2X_BRESP_ERR_INT_RAW_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("AHB2AXI_BRESP_ERR_INT_RAW")
+            .field(
+                "cpu_icm_h2x_bresp_err_int_raw",
+                &format_args!("{}", self.cpu_icm_h2x_bresp_err_int_raw().bit()),
+            )
+            .finish()
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<AHB2AXI_BRESP_ERR_INT_RAW_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - the raw interrupt status of bresp error, triggered when if bresp err occurs in post write mode in ahb2axi."]
+    #[inline(always)]
+    #[must_use]
+    pub fn cpu_icm_h2x_bresp_err_int_raw(
+        &mut self,
+    ) -> CPU_ICM_H2X_BRESP_ERR_INT_RAW_W<AHB2AXI_BRESP_ERR_INT_RAW_SPEC> {
+        CPU_ICM_H2X_BRESP_ERR_INT_RAW_W::new(self, 0)
+    }
+    #[doc = r" Writes raw bits to the register."]
+    #[doc = r""]
+    #[doc = r" # Safety"]
+    #[doc = r""]
+    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
+#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb2axi_bresp_err_int_raw::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ahb2axi_bresp_err_int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct AHB2AXI_BRESP_ERR_INT_RAW_SPEC;
+impl crate::RegisterSpec for AHB2AXI_BRESP_ERR_INT_RAW_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ahb2axi_bresp_err_int_raw::R`](R) reader structure"]
+impl crate::Readable for AHB2AXI_BRESP_ERR_INT_RAW_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`ahb2axi_bresp_err_int_raw::W`](W) writer structure"]
+impl crate::Writable for AHB2AXI_BRESP_ERR_INT_RAW_SPEC {
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets AHB2AXI_BRESP_ERR_INT_RAW to value 0"]
+impl crate::Resettable for AHB2AXI_BRESP_ERR_INT_RAW_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

esp32p4/src/hp_sys/ahb2axi_bresp_err_int_st.rs

@@ -0,0 +1,39 @@
+#[doc = "Register `AHB2AXI_BRESP_ERR_INT_ST` reader"]
+pub type R = crate::R<AHB2AXI_BRESP_ERR_INT_ST_SPEC>;
+#[doc = "Field `CPU_ICM_H2X_BRESP_ERR_INT_ST` reader - the masked interrupt status of cpu_icm_h2x_bresp_err"]
+pub type CPU_ICM_H2X_BRESP_ERR_INT_ST_R = crate::BitReader;
+impl R {
+    #[doc = "Bit 31 - the masked interrupt status of cpu_icm_h2x_bresp_err"]
+    #[inline(always)]
+    pub fn cpu_icm_h2x_bresp_err_int_st(&self) -> CPU_ICM_H2X_BRESP_ERR_INT_ST_R {
+        CPU_ICM_H2X_BRESP_ERR_INT_ST_R::new(((self.bits >> 31) & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("AHB2AXI_BRESP_ERR_INT_ST")
+            .field(
+                "cpu_icm_h2x_bresp_err_int_st",
+                &format_args!("{}", self.cpu_icm_h2x_bresp_err_int_st().bit()),
+            )
+            .finish()
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<AHB2AXI_BRESP_ERR_INT_ST_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
+#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ahb2axi_bresp_err_int_st::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct AHB2AXI_BRESP_ERR_INT_ST_SPEC;
+impl crate::RegisterSpec for AHB2AXI_BRESP_ERR_INT_ST_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ahb2axi_bresp_err_int_st::R`](R) reader structure"]
+impl crate::Readable for AHB2AXI_BRESP_ERR_INT_ST_SPEC {}
+#[doc = "`reset()` method sets AHB2AXI_BRESP_ERR_INT_ST to value 0"]
+impl crate::Resettable for AHB2AXI_BRESP_ERR_INT_ST_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}

esp32p4/src/hp_sys/bitscrambler_peri_sel.rs

@@ -0,0 +1,89 @@
+#[doc = "Register `BITSCRAMBLER_PERI_SEL` reader"]
+pub type R = crate::R<BITSCRAMBLER_PERI_SEL_SPEC>;
+#[doc = "Register `BITSCRAMBLER_PERI_SEL` writer"]
+pub type W = crate::W<BITSCRAMBLER_PERI_SEL_SPEC>;
+#[doc = "Field `BITSCRAMBLER_PERI_RX_SEL` reader - Set this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none"]
+pub type BITSCRAMBLER_PERI_RX_SEL_R = crate::FieldReader;
+#[doc = "Field `BITSCRAMBLER_PERI_RX_SEL` writer - Set this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none"]
+pub type BITSCRAMBLER_PERI_RX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `BITSCRAMBLER_PERI_TX_SEL` reader - Set this field to sel peri with DMA TX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none"]
+pub type BITSCRAMBLER_PERI_TX_SEL_R = crate::FieldReader;
+#[doc = "Field `BITSCRAMBLER_PERI_TX_SEL` writer - Set this field to sel peri with DMA TX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none"]
+pub type BITSCRAMBLER_PERI_TX_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - Set this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none"]
+    #[inline(always)]
+    pub fn bitscrambler_peri_rx_sel(&self) -> BITSCRAMBLER_PERI_RX_SEL_R {
+        BITSCRAMBLER_PERI_RX_SEL_R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - Set this field to sel peri with DMA TX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none"]
+    #[inline(always)]
+    pub fn bitscrambler_peri_tx_sel(&self) -> BITSCRAMBLER_PERI_TX_SEL_R {
+        BITSCRAMBLER_PERI_TX_SEL_R::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("BITSCRAMBLER_PERI_SEL")
+            .field(
+                "bitscrambler_peri_rx_sel",
+                &format_args!("{}", self.bitscrambler_peri_rx_sel().bits()),
+            )
+            .field(
+                "bitscrambler_peri_tx_sel",
+                &format_args!("{}", self.bitscrambler_peri_tx_sel().bits()),
+            )
+            .finish()
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<BITSCRAMBLER_PERI_SEL_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Set this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none"]
+    #[inline(always)]
+    #[must_use]
+    pub fn bitscrambler_peri_rx_sel(
+        &mut self,
+    ) -> BITSCRAMBLER_PERI_RX_SEL_W<BITSCRAMBLER_PERI_SEL_SPEC> {
+        BITSCRAMBLER_PERI_RX_SEL_W::new(self, 0)
+    }
+    #[doc = "Bits 4:7 - Set this field to sel peri with DMA TX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none"]
+    #[inline(always)]
+    #[must_use]
+    pub fn bitscrambler_peri_tx_sel(
+        &mut self,
+    ) -> BITSCRAMBLER_PERI_TX_SEL_W<BITSCRAMBLER_PERI_SEL_SPEC> {
+        BITSCRAMBLER_PERI_TX_SEL_W::new(self, 4)
+    }
+    #[doc = r" Writes raw bits to the register."]
+    #[doc = r""]
+    #[doc = r" # Safety"]
+    #[doc = r""]
+    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
+#[doc = "Bitscrambler Peri Sel\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bitscrambler_peri_sel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bitscrambler_peri_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct BITSCRAMBLER_PERI_SEL_SPEC;
+impl crate::RegisterSpec for BITSCRAMBLER_PERI_SEL_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`bitscrambler_peri_sel::R`](R) reader structure"]
+impl crate::Readable for BITSCRAMBLER_PERI_SEL_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`bitscrambler_peri_sel::W`](W) writer structure"]
+impl crate::Writable for BITSCRAMBLER_PERI_SEL_SPEC {
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets BITSCRAMBLER_PERI_SEL to value 0xff"]
+impl crate::Resettable for BITSCRAMBLER_PERI_SEL_SPEC {
+    const RESET_VALUE: Self::Ux = 0xff;
+}

esp32p4/src/hp_sys/cache_apb_postw_en.rs

@@ -0,0 +1,66 @@
+#[doc = "Register `CACHE_APB_POSTW_EN` reader"]
+pub type R = crate::R<CACHE_APB_POSTW_EN_SPEC>;
+#[doc = "Register `CACHE_APB_POSTW_EN` writer"]
+pub type W = crate::W<CACHE_APB_POSTW_EN_SPEC>;
+#[doc = "Field `REG_CACHE_APB_POSTW_EN` reader - cache apb register interface post write enable, 1 will speed up write, but will take some time to update value to register"]
+pub type REG_CACHE_APB_POSTW_EN_R = crate::BitReader;
+#[doc = "Field `REG_CACHE_APB_POSTW_EN` writer - cache apb register interface post write enable, 1 will speed up write, but will take some time to update value to register"]
+pub type REG_CACHE_APB_POSTW_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - cache apb register interface post write enable, 1 will speed up write, but will take some time to update value to register"]
+    #[inline(always)]
+    pub fn reg_cache_apb_postw_en(&self) -> REG_CACHE_APB_POSTW_EN_R {
+        REG_CACHE_APB_POSTW_EN_R::new((self.bits & 1) != 0)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("CACHE_APB_POSTW_EN")
+            .field(
+                "reg_cache_apb_postw_en",
+                &format_args!("{}", self.reg_cache_apb_postw_en().bit()),
+            )
+            .finish()
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for crate::generic::Reg<CACHE_APB_POSTW_EN_SPEC> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        core::fmt::Debug::fmt(&self.read(), f)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - cache apb register interface post write enable, 1 will speed up write, but will take some time to update value to register"]
+    #[inline(always)]
+    #[must_use]
+    pub fn reg_cache_apb_postw_en(&mut self) -> REG_CACHE_APB_POSTW_EN_W<CACHE_APB_POSTW_EN_SPEC> {
+        REG_CACHE_APB_POSTW_EN_W::new(self, 0)
+    }
+    #[doc = r" Writes raw bits to the register."]
+    #[doc = r""]
+    #[doc = r" # Safety"]
+    #[doc = r""]
+    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
+    #[inline(always)]
+    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
+        self.bits = bits;
+        self
+    }
+}
+#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_apb_postw_en::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cache_apb_postw_en::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CACHE_APB_POSTW_EN_SPEC;
+impl crate::RegisterSpec for CACHE_APB_POSTW_EN_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`cache_apb_postw_en::R`](R) reader structure"]
+impl crate::Readable for CACHE_APB_POSTW_EN_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cache_apb_postw_en::W`](W) writer structure"]
+impl crate::Writable for CACHE_APB_POSTW_EN_SPEC {
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
+}
+#[doc = "`reset()` method sets CACHE_APB_POSTW_EN to value 0"]
+impl crate::Resettable for CACHE_APB_POSTW_EN_SPEC {
+    const RESET_VALUE: Self::Ux = 0;
+}