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Update pacs
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bugadani committed Feb 5, 2025
1 parent 6fbc923 commit 31bd146
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Showing 6 changed files with 21 additions and 27 deletions.
14 changes: 7 additions & 7 deletions esp-hal/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -56,13 +56,13 @@ ufmt-write = "0.1.0"
# IMPORTANT:
# Each supported device MUST have its PAC included below along with a
# corresponding feature.
esp32 = { version = "0.35.0", features = ["critical-section", "rt"], optional = true }
esp32c2 = { version = "0.24.0", features = ["critical-section", "rt"], optional = true }
esp32c3 = { version = "0.27.0", features = ["critical-section", "rt"], optional = true }
esp32c6 = { version = "0.18.0", features = ["critical-section", "rt"], optional = true }
esp32h2 = { version = "0.14.0", features = ["critical-section", "rt"], optional = true }
esp32s2 = { version = "0.26.0", features = ["critical-section", "rt"], optional = true }
esp32s3 = { version = "0.30.0", features = ["critical-section", "rt"], optional = true }
esp32 = { version = "0.35.0", features = ["critical-section", "rt"], git = "https://github.com/esp-rs/esp-pacs", rev = "e5fc973", optional = true }
esp32c2 = { version = "0.24.0", features = ["critical-section", "rt"], git = "https://github.com/esp-rs/esp-pacs", rev = "e5fc973", optional = true }
esp32c3 = { version = "0.27.0", features = ["critical-section", "rt"], git = "https://github.com/esp-rs/esp-pacs", rev = "e5fc973", optional = true }
esp32c6 = { version = "0.18.0", features = ["critical-section", "rt"], git = "https://github.com/esp-rs/esp-pacs", rev = "e5fc973", optional = true }
esp32h2 = { version = "0.14.0", features = ["critical-section", "rt"], git = "https://github.com/esp-rs/esp-pacs", rev = "e5fc973", optional = true }
esp32s2 = { version = "0.26.0", features = ["critical-section", "rt"], git = "https://github.com/esp-rs/esp-pacs", rev = "e5fc973", optional = true }
esp32s3 = { version = "0.30.0", features = ["critical-section", "rt"], git = "https://github.com/esp-rs/esp-pacs", rev = "e5fc973", optional = true }

[target.'cfg(target_arch = "riscv32")'.dependencies]
riscv = { version = "0.12.1" }
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9 changes: 4 additions & 5 deletions esp-hal/src/clock/clocks_ll/esp32.rs
Original file line number Diff line number Diff line change
Expand Up @@ -294,13 +294,12 @@ pub(super) fn enable_wifi(enable: bool) {
}

pub(super) fn reset_mac() {
const SYSTEM_MAC_RST: u8 = 1 << 2;
DPORT::regs()
.core_rst_en()
.modify(|r, w| unsafe { w.core_rst().bits(r.core_rst().bits() | SYSTEM_MAC_RST) });
.wifi_rst_en()
.modify(|_, w| w.mac_rst().set_bit());
DPORT::regs()
.core_rst_en()
.modify(|r, w| unsafe { w.core_rst().bits(r.core_rst().bits() & !SYSTEM_MAC_RST) });
.wifi_rst_en()
.modify(|_, w| w.mac_rst().clear_bit());
}

pub(super) fn init_clocks() {
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10 changes: 4 additions & 6 deletions esp-hal/src/clock/clocks_ll/esp32c2.rs
Original file line number Diff line number Diff line change
Expand Up @@ -199,13 +199,12 @@ pub(super) fn enable_wifi(_: bool) {
}

pub(super) fn reset_mac() {
const SYSTEM_MAC_RST: u32 = 1 << 2;
APB_CTRL::regs()
.wifi_rst_en()
.modify(|r, w| unsafe { w.wifi_rst().bits(r.wifi_rst().bits() | SYSTEM_MAC_RST) });
.modify(|_, w| w.mac_rst().set_bit());
APB_CTRL::regs()
.wifi_rst_en()
.modify(|r, w| unsafe { w.wifi_rst().bits(r.wifi_rst().bits() & !SYSTEM_MAC_RST) });
.modify(|_, w| w.mac_rst().clear_bit());
}

pub(super) fn init_clocks() {
Expand Down Expand Up @@ -248,11 +247,10 @@ pub(super) fn ble_rtc_clk_init() {
}

pub(super) fn reset_rpa() {
const BLE_RPA_REST_BIT: u32 = 1 << 27;
APB_CTRL::regs()
.wifi_rst_en()
.modify(|r, w| unsafe { w.bits(r.bits() | BLE_RPA_REST_BIT) });
.modify(|_, w| w.ble_rpa_rst().set_bit());
APB_CTRL::regs()
.wifi_rst_en()
.modify(|r, w| unsafe { w.bits(r.bits() & !BLE_RPA_REST_BIT) });
.modify(|_, w| w.ble_rpa_rst().clear_bit());
}
5 changes: 2 additions & 3 deletions esp-hal/src/clock/clocks_ll/esp32c3.rs
Original file line number Diff line number Diff line change
Expand Up @@ -259,13 +259,12 @@ pub(super) fn enable_bt(_: bool) {
}

pub(super) fn reset_mac() {
const SYSTEM_MAC_RST: u32 = 1 << 2;
APB_CTRL::regs()
.wifi_rst_en()
.modify(|r, w| unsafe { w.wifi_rst().bits(r.wifi_rst().bits() | SYSTEM_MAC_RST) });
.modify(|_, w| w.mac_rst().set_bit());
APB_CTRL::regs()
.wifi_rst_en()
.modify(|r, w| unsafe { w.wifi_rst().bits(r.wifi_rst().bits() & !SYSTEM_MAC_RST) });
.modify(|_, w| w.mac_rst().clear_bit());
}

pub(super) fn init_clocks() {
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5 changes: 2 additions & 3 deletions esp-hal/src/clock/clocks_ll/esp32s2.rs
Original file line number Diff line number Diff line change
Expand Up @@ -72,13 +72,12 @@ pub(super) fn enable_wifi(enable: bool) {
}

pub(super) fn reset_mac() {
const SYSTEM_MAC_RST: u32 = 1 << 2;
SYSCON::regs()
.wifi_rst_en()
.modify(|r, w| unsafe { w.wifi_rst().bits(r.wifi_rst().bits() | SYSTEM_MAC_RST) });
.modify(|_, w| w.mac_rst().set_bit());
SYSCON::regs()
.wifi_rst_en()
.modify(|r, w| unsafe { w.wifi_rst().bits(r.wifi_rst().bits() & !SYSTEM_MAC_RST) });
.modify(|_, w| w.mac_rst().clear_bit());
}

pub(super) fn init_clocks() {
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5 changes: 2 additions & 3 deletions esp-hal/src/clock/clocks_ll/esp32s3.rs
Original file line number Diff line number Diff line change
Expand Up @@ -57,13 +57,12 @@ pub(super) fn enable_wifi(_: bool) {
}

pub(super) fn reset_mac() {
const SYSTEM_MAC_RST: u32 = 1 << 2;
APB_CTRL::regs()
.wifi_rst_en()
.modify(|r, w| unsafe { w.bits(r.bits() | SYSTEM_MAC_RST) });
.modify(|_, w| w.mac_rst().set_bit());
APB_CTRL::regs()
.wifi_rst_en()
.modify(|r, w| unsafe { w.bits(r.bits() & !SYSTEM_MAC_RST) });
.modify(|_, w| w.mac_rst().clear_bit());
}

pub(super) fn init_clocks() {
Expand Down

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