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Replace trait with driver
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@bugadani
bugadani committed Feb 5, 2025
1 parent 9d51284 commit 1d43fb6
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Showing 25 changed files with 367 additions and 694 deletions.
1 change: 1 addition & 0 deletions esp-hal/CHANGELOG.md
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Original file line number Diff line number Diff line change
Expand Up @@ -36,6 +36,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Migrate AES driver to DMA move API (#3084)
- Removed features `psram-quad` and `psram-octal` - replaced by `psram` and the `ESP_HAL_CONFIG_PSRAM_MODE` (`quad`/`octal`) (#3001)
- The `esp_hal::time` module no longer reexports `fugit` types (#3083)
- The `system::RadioClockController` trait has been replaced by the `clock::RadioClockController` struct. (#3100)

- I2C: Async functions are postfixed with `_async`, non-async functions are available in async-mode (#3056)

Expand Down
106 changes: 35 additions & 71 deletions esp-hal/src/clock/clocks_ll/esp32.rs
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Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
use crate::{
clock::{Clock, PllClock, XtalClock},
peripherals::DPORT,
rom::regi2c_write,
};

Expand Down Expand Up @@ -254,90 +255,45 @@ fn esp32_update_cpu_freq(mhz: u32) {
}
}

use crate::{
peripherals::DPORT,
system::{RadioClockController, RadioPeripherals},
};

const DPORT_WIFI_CLK_WIFI_BT_COMMON_M: u32 = 0x000003c9;
const DPORT_WIFI_CLK_WIFI_EN_M: u32 = 0x00000406;
const DPORT_WIFI_CLK_BT_EN_M: u32 = 0x00030800;

impl RadioClockController for crate::peripherals::RADIO_CLK {
fn enable(&mut self, peripheral: RadioPeripherals) {
match peripheral {
RadioPeripherals::Phy => enable_phy(),
RadioPeripherals::Bt => bt_clock_enable(),
RadioPeripherals::Wifi => wifi_clock_enable(),
}
}

fn disable(&mut self, peripheral: RadioPeripherals) {
match peripheral {
RadioPeripherals::Phy => disable_phy(),
RadioPeripherals::Bt => bt_clock_disable(),
RadioPeripherals::Wifi => wifi_clock_disable(),
}
}

fn reset_mac(&mut self) {
reset_mac();
}

fn init_clocks(&mut self) {
init_clocks();
}

fn ble_rtc_clk_init(&mut self) {
// nothing for this target
}

fn reset_rpa(&mut self) {
// nothing for this target
}
}

fn enable_phy() {
pub(super) fn enable_phy(enable: bool) {
// `periph_ll_wifi_bt_module_enable_clk_clear_rst`
DPORT::regs()
.wifi_clk_en()
.modify(|r, w| unsafe { w.bits(r.bits() | DPORT_WIFI_CLK_WIFI_BT_COMMON_M) });
}

fn disable_phy() {
// `periph_ll_wifi_bt_module_disable_clk_set_rst`
DPORT::regs()
.wifi_clk_en()
.modify(|r, w| unsafe { w.bits(r.bits() & !DPORT_WIFI_CLK_WIFI_BT_COMMON_M) });
}

fn bt_clock_enable() {
DPORT::regs()
.wifi_clk_en()
.modify(|r, w| unsafe { w.bits(r.bits() | DPORT_WIFI_CLK_BT_EN_M) });
DPORT::regs().wifi_clk_en().modify(|r, w| unsafe {
if enable {
w.bits(r.bits() | DPORT_WIFI_CLK_WIFI_BT_COMMON_M)
} else {
w.bits(r.bits() & !DPORT_WIFI_CLK_WIFI_BT_COMMON_M)
}
});
}

fn bt_clock_disable() {
DPORT::regs()
.wifi_clk_en()
.modify(|r, w| unsafe { w.bits(r.bits() & !DPORT_WIFI_CLK_BT_EN_M) });
pub(super) fn enable_bt(enable: bool) {
DPORT::regs().wifi_clk_en().modify(|r, w| unsafe {
if enable {
w.bits(r.bits() | DPORT_WIFI_CLK_BT_EN_M)
} else {
w.bits(r.bits() & !DPORT_WIFI_CLK_BT_EN_M)
}
});
}

fn wifi_clock_enable() {
pub(super) fn enable_wifi(enable: bool) {
// `periph_ll_wifi_module_enable_clk_clear_rst`
DPORT::regs()
.wifi_clk_en()
.modify(|r, w| unsafe { w.bits(r.bits() | DPORT_WIFI_CLK_WIFI_EN_M) });
}

fn wifi_clock_disable() {
// `periph_ll_wifi_module_disable_clk_set_rst`
DPORT::regs()
.wifi_clk_en()
.modify(|r, w| unsafe { w.bits(r.bits() & !DPORT_WIFI_CLK_WIFI_EN_M) });
DPORT::regs().wifi_clk_en().modify(|r, w| unsafe {
if enable {
w.bits(r.bits() | DPORT_WIFI_CLK_WIFI_EN_M)
} else {
w.bits(r.bits() & !DPORT_WIFI_CLK_WIFI_EN_M)
}
});
}

fn reset_mac() {
pub(super) fn reset_mac() {
const SYSTEM_MAC_RST: u8 = 1 << 2;
DPORT::regs()
.core_rst_en()
Expand All @@ -347,7 +303,7 @@ fn reset_mac() {
.modify(|r, w| unsafe { w.core_rst().bits(r.core_rst().bits() & !SYSTEM_MAC_RST) });
}

fn init_clocks() {
pub(super) fn init_clocks() {
// esp-idf assumes all clocks are enabled by default, and disables the following
// bits:
//
Expand Down Expand Up @@ -375,3 +331,11 @@ fn init_clocks() {
.wifi_clk_en()
.write(|w| unsafe { w.bits(u32::MAX) });
}

pub(super) fn ble_rtc_clk_init() {
// nothing for this target
}

pub(super) fn reset_rpa() {
// nothing for this target
}
67 changes: 16 additions & 51 deletions esp-hal/src/clock/clocks_ll/esp32c2.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,6 @@ use crate::{
clock::{ApbClock, Clock, CpuClock, PllClock, XtalClock},
peripherals::{APB_CTRL, MODEM_CLKRST},
rom::{regi2c_write, regi2c_write_mask},
system::{RadioClockController, RadioPeripherals},
};

const I2C_BBPLL: u32 = 0x66;
Expand Down Expand Up @@ -177,63 +176,29 @@ const SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M: u32 = 0x78078F;
// SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030
const SYSTEM_WIFI_CLK_EN: u32 = 0x00FB9FCF;

impl RadioClockController for crate::peripherals::RADIO_CLK {
fn enable(&mut self, peripheral: RadioPeripherals) {
match peripheral {
RadioPeripherals::Phy => enable_phy(),
RadioPeripherals::Bt => common_wifi_bt_clock_enable(),
RadioPeripherals::Wifi => common_wifi_bt_clock_enable(),
}
}

fn disable(&mut self, peripheral: RadioPeripherals) {
match peripheral {
RadioPeripherals::Phy => disable_phy(),
RadioPeripherals::Bt => common_wifi_bt_clock_disable(),
RadioPeripherals::Wifi => common_wifi_bt_clock_disable(),
}
}

fn reset_mac(&mut self) {
reset_mac();
}

fn init_clocks(&mut self) {
init_clocks();
}

fn ble_rtc_clk_init(&mut self) {
ble_rtc_clk_init();
}

fn reset_rpa(&mut self) {
reset_rpa();
}
}

fn enable_phy() {
pub(super) fn enable_phy(enable: bool) {
// `periph_ll_wifi_bt_module_enable_clk_clear_rst`
APB_CTRL::regs()
.wifi_clk_en()
.modify(|r, w| unsafe { w.bits(r.bits() | SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M) });
}

fn disable_phy() {
// `periph_ll_wifi_bt_module_disable_clk_set_rst`
APB_CTRL::regs()
.wifi_clk_en()
.modify(|r, w| unsafe { w.bits(r.bits() & !SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M) });
APB_CTRL::regs().wifi_clk_en().modify(|r, w| unsafe {
if enable {
w.bits(r.bits() | SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M)
} else {
w.bits(r.bits() & !SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M)
}
});
}

fn common_wifi_bt_clock_enable() {
pub(super) fn enable_bt(_: bool) {
// `periph_ll_wifi_module_enable_clk_clear_rst`, no-op
// `periph_ll_wifi_module_disable_clk_clear_rst`, no-op
}

fn common_wifi_bt_clock_disable() {
pub(super) fn enable_wifi(_: bool) {
// `periph_ll_wifi_module_enable_clk_clear_rst`, no-op
// `periph_ll_wifi_module_disable_clk_clear_rst`, no-op
}

fn reset_mac() {
pub(super) fn reset_mac() {
const SYSTEM_MAC_RST: u32 = 1 << 2;
APB_CTRL::regs()
.wifi_rst_en()
Expand All @@ -243,7 +208,7 @@ fn reset_mac() {
.modify(|r, w| unsafe { w.wifi_rst().bits(r.wifi_rst().bits() & !SYSTEM_MAC_RST) });
}

fn init_clocks() {
pub(super) fn init_clocks() {
// from `esp_perip_clk_init`
const SYSTEM_WIFI_CLK_UNUSED_BIT5: u32 = 1 << 5;
const SYSTEM_WIFI_CLK_UNUSED_BIT12: u32 = 1 << 12;
Expand All @@ -254,7 +219,7 @@ fn init_clocks() {
.modify(|r, w| unsafe { w.bits(r.bits() & !WIFI_BT_SDIO_CLK | SYSTEM_WIFI_CLK_EN) });
}

fn ble_rtc_clk_init() {
pub(super) fn ble_rtc_clk_init() {
let modem_clkrst = MODEM_CLKRST::regs();
modem_clkrst
.modem_lp_timer_conf()
Expand Down Expand Up @@ -282,7 +247,7 @@ fn ble_rtc_clk_init() {
.modify(|_, w| w.etm_clk_sel().clear_bit());
}

fn reset_rpa() {
pub(super) fn reset_rpa() {
const BLE_RPA_REST_BIT: u32 = 1 << 27;
APB_CTRL::regs()
.wifi_rst_en()
Expand Down
71 changes: 22 additions & 49 deletions esp-hal/src/clock/clocks_ll/esp32c3.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,6 @@ use crate::{
clock::{ApbClock, Clock, CpuClock, PllClock, XtalClock},
peripherals::{APB_CTRL, LPWR},
rom::{regi2c_write, regi2c_write_mask},
system::{RadioClockController, RadioPeripherals},
};

const I2C_BBPLL: u32 = 0x66;
Expand Down Expand Up @@ -237,63 +236,29 @@ const SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M: u32 = 0x78078F;
// SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030
const SYSTEM_WIFI_CLK_EN: u32 = 0x00FB9FCF;

impl RadioClockController for crate::peripherals::RADIO_CLK {
fn enable(&mut self, peripheral: RadioPeripherals) {
match peripheral {
RadioPeripherals::Phy => enable_phy(),
RadioPeripherals::Bt => common_wifi_bt_clock_enable(),
RadioPeripherals::Wifi => common_wifi_bt_clock_enable(),
}
}

fn disable(&mut self, peripheral: RadioPeripherals) {
match peripheral {
RadioPeripherals::Phy => disable_phy(),
RadioPeripherals::Bt => common_wifi_bt_clock_disable(),
RadioPeripherals::Wifi => common_wifi_bt_clock_disable(),
}
}

fn reset_mac(&mut self) {
reset_mac();
}

fn init_clocks(&mut self) {
init_clocks();
}

fn ble_rtc_clk_init(&mut self) {
// nothing for this target
}

fn reset_rpa(&mut self) {
// nothing for this target
}
}

fn enable_phy() {
pub(super) fn enable_phy(enable: bool) {
// `periph_ll_wifi_bt_module_enable_clk_clear_rst`
APB_CTRL::regs()
.wifi_clk_en()
.modify(|r, w| unsafe { w.bits(r.bits() | SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M) });
}

fn disable_phy() {
// `periph_ll_wifi_bt_module_disable_clk_set_rst`
APB_CTRL::regs()
.wifi_clk_en()
.modify(|r, w| unsafe { w.bits(r.bits() & !SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M) });
APB_CTRL::regs().wifi_clk_en().modify(|r, w| unsafe {
if enable {
w.bits(r.bits() | SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M)
} else {
w.bits(r.bits() & !SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M)
}
});
}

fn common_wifi_bt_clock_enable() {
pub(super) fn enable_wifi(_: bool) {
// `periph_ll_wifi_module_enable_clk_clear_rst`, no-op
// `periph_ll_wifi_module__clk_clear_rst`, no-op
}

fn common_wifi_bt_clock_disable() {
pub(super) fn enable_bt(_: bool) {
// `periph_ll_wifi_module_enable_clk_clear_rst`, no-op
// `periph_ll_wifi_module__clk_clear_rst`, no-op
}

fn reset_mac() {
pub(super) fn reset_mac() {
const SYSTEM_MAC_RST: u32 = 1 << 2;
APB_CTRL::regs()
.wifi_rst_en()
Expand All @@ -303,7 +268,7 @@ fn reset_mac() {
.modify(|r, w| unsafe { w.wifi_rst().bits(r.wifi_rst().bits() & !SYSTEM_MAC_RST) });
}

fn init_clocks() {
pub(super) fn init_clocks() {
// undo the power down in base_settings (esp32c3_sleep)
LPWR::regs()
.dig_iso()
Expand All @@ -322,3 +287,11 @@ fn init_clocks() {
.wifi_clk_en()
.modify(|r, w| unsafe { w.bits(r.bits() & !WIFI_BT_SDIO_CLK | SYSTEM_WIFI_CLK_EN) });
}

pub(super) fn ble_rtc_clk_init() {
// nothing for this target
}

pub(super) fn reset_rpa() {
// nothing for this target
}
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