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Blackbox all whiteboxes after synthesis
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This prevents issues like processes in whiteboxes triggering an error in
the JSON backend.

Signed-off-by: gatecat <[email protected]>
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gatecat committed Mar 17, 2021
1 parent c8b45a4 commit cae905f
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Showing 16 changed files with 24 additions and 9 deletions.
1 change: 1 addition & 0 deletions techlibs/achronix/synth_achronix.cc
Original file line number Diff line number Diff line change
Expand Up @@ -173,6 +173,7 @@ struct SynthAchronixPass : public ScriptPass {
run("hierarchy -check");
run("stat");
run("check -noinit");
run("blackbox =A:whitebox");
}

if (check_label("vout"))
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1 change: 1 addition & 0 deletions techlibs/anlogic/synth_anlogic.cc
Original file line number Diff line number Diff line change
Expand Up @@ -211,6 +211,7 @@ struct SynthAnlogicPass : public ScriptPass
run("hierarchy -check");
run("stat");
run("check -noinit");
run("blackbox =A:whitebox");
}

if (check_label("edif"))
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1 change: 1 addition & 0 deletions techlibs/coolrunner2/synth_coolrunner2.cc
Original file line number Diff line number Diff line change
Expand Up @@ -192,6 +192,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
run("hierarchy -check");
run("stat");
run("check -noinit");
run("blackbox =A:whitebox");
}

if (check_label("json"))
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1 change: 1 addition & 0 deletions techlibs/easic/synth_easic.cc
Original file line number Diff line number Diff line change
Expand Up @@ -175,6 +175,7 @@ struct SynthEasicPass : public ScriptPass
run("hierarchy -check");
run("stat");
run("check -noinit");
run("blackbox =A:whitebox");
}

if (check_label("vlog"))
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1 change: 1 addition & 0 deletions techlibs/ecp5/synth_ecp5.cc
Original file line number Diff line number Diff line change
Expand Up @@ -385,6 +385,7 @@ struct SynthEcp5Pass : public ScriptPass
run("hierarchy -check");
run("stat");
run("check -noinit");
run("blackbox =A:whitebox");
}

if (check_label("blif"))
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1 change: 1 addition & 0 deletions techlibs/efinix/synth_efinix.cc
Original file line number Diff line number Diff line change
Expand Up @@ -213,6 +213,7 @@ struct SynthEfinixPass : public ScriptPass
run("hierarchy -check");
run("stat");
run("check -noinit");
run("blackbox =A:whitebox");
}

if (check_label("edif"))
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1 change: 1 addition & 0 deletions techlibs/gowin/synth_gowin.cc
Original file line number Diff line number Diff line change
Expand Up @@ -289,6 +289,7 @@ struct SynthGowinPass : public ScriptPass
run("hierarchy -check");
run("stat");
run("check -noinit");
run("blackbox =A:whitebox");
}

if (check_label("vout"))
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1 change: 1 addition & 0 deletions techlibs/greenpak4/synth_greenpak4.cc
Original file line number Diff line number Diff line change
Expand Up @@ -196,6 +196,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
run("hierarchy -check");
run("stat");
run("check -noinit");
run("blackbox =A:whitebox");
}

if (check_label("json"))
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1 change: 1 addition & 0 deletions techlibs/ice40/synth_ice40.cc
Original file line number Diff line number Diff line change
Expand Up @@ -417,6 +417,7 @@ struct SynthIce40Pass : public ScriptPass
run("hierarchy -check");
run("stat");
run("check -noinit");
run("blackbox =A:whitebox");
}

if (check_label("blif"))
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1 change: 1 addition & 0 deletions techlibs/intel/synth_intel.cc
Original file line number Diff line number Diff line change
Expand Up @@ -233,6 +233,7 @@ struct SynthIntelPass : public ScriptPass {
run("hierarchy -check");
run("stat");
run("check -noinit");
run("blackbox =A:whitebox");
}

if (check_label("vqm")) {
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1 change: 1 addition & 0 deletions techlibs/intel_alm/synth_intel_alm.cc
Original file line number Diff line number Diff line change
Expand Up @@ -274,6 +274,7 @@ struct SynthIntelALMPass : public ScriptPass {
run("hierarchy -check");
run("stat");
run("check");
run("blackbox =A:whitebox");
}

if (check_label("quartus")) {
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1 change: 1 addition & 0 deletions techlibs/machxo2/synth_machxo2.cc
Original file line number Diff line number Diff line change
Expand Up @@ -212,6 +212,7 @@ struct SynthMachXO2Pass : public ScriptPass
{
run("hierarchy -check");
run("stat");
run("blackbox =A:whitebox");
}

if (check_label("blif"))
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1 change: 1 addition & 0 deletions techlibs/nexus/synth_nexus.cc
Original file line number Diff line number Diff line change
Expand Up @@ -406,6 +406,7 @@ struct SynthNexusPass : public ScriptPass
run("hierarchy -check");
run("stat");
run("check -noinit");
run("blackbox =A:whitebox");
}

if (check_label("json"))
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1 change: 1 addition & 0 deletions techlibs/sf2/synth_sf2.cc
Original file line number Diff line number Diff line change
Expand Up @@ -228,6 +228,7 @@ struct SynthSf2Pass : public ScriptPass
run("hierarchy -check");
run("stat");
run("check -noinit");
run("blackbox =A:whitebox");
}

if (check_label("edif"))
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1 change: 1 addition & 0 deletions techlibs/xilinx/synth_xilinx.cc
Original file line number Diff line number Diff line change
Expand Up @@ -662,6 +662,7 @@ struct SynthXilinxPass : public ScriptPass
run("hierarchy -check");
run("stat -tech xilinx");
run("check -noinit");
run("blackbox =A:whitebox");
}

if (check_label("edif")) {
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18 changes: 9 additions & 9 deletions tests/arch/ecp5/mux.ys
Original file line number Diff line number Diff line change
Expand Up @@ -15,9 +15,9 @@ proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 1 t:L6MUX21
select -assert-count 4 t:LUT4
select -assert-count 2 t:PFUMX
select -assert-max 1 t:L6MUX21
select -assert-max 4 t:LUT4
select -assert-max 2 t:PFUMX

select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D

Expand All @@ -27,9 +27,9 @@ proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 1 t:L6MUX21
select -assert-count 7 t:LUT4
select -assert-count 2 t:PFUMX
select -assert-max 1 t:L6MUX21
select -assert-max 7 t:LUT4
select -assert-max 2 t:PFUMX

select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D

Expand All @@ -39,8 +39,8 @@ proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-count 8 t:L6MUX21
select -assert-count 26 t:LUT4
select -assert-count 12 t:PFUMX
select -assert-max 12 t:L6MUX21
select -assert-max 34 t:LUT4
select -assert-max 17 t:PFUMX

select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D

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